AM79C930VCW datasheet(98/161 Pages) AMD

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P R E L I M I N A R Y

Am79C930

TIR15: Byte Count Limit MSB

This register is the Byte Count Limit MSB register.

Bit

Name

Reset Value

Description

7–4

Reserved

–

Reserved. Must be written as a 0. Reads of this bit produce

undefined data.

3–0

BCLT[11:8]

Byte Count Limit. Upper 4 bits of byte count limit for both transmit

and receive operations, depending upon which operation is cur-

rently occurring. During transmit operations, when the byte count

limit is reached, an interrupt to the 80188 controller will be gener-

ated if the TXBCNT interrupt has been unmasked. During TX, the

byte counter counts all bytes beginning with the first byte after the

SFD field has been detected and does not count the CRC bytes ap-

pended to the TX frame. During RX, when the byte count limit is

reached, an interrupt to the 80188 controller will be generated if the

RXBCNT interrupt has been unmasked. During RX, the byte

counter counts all bytes that follow the Start of Frame delimiter.

Byte count limit has no effect on state machine or FIFO operations.

TIR16: Receiver Control

This register is the Receiver Control register. This regis-

ter allows basic control of the receive function.

Bit

Name

Reset Value

Description

RXRES

Receive Reset. When this bit is set to 1, the internal Receive Reset

signal is asserted. When this bit is set to 0, the internal Receive Re-

set signal is deasserted. The Receive FIFO is not reset by RXRES.

RXFR

Receive FIFO Reset. When this bit is set to 1, the internal Receive

FIFO Reset signal is asserted. When this bit is set to 0, the internal

Receive FIFO Reset signal is deasserted.

5–1

Reserved

–

Reserved. Must be written as a 0. Reads of this bit produce

undefined data.

RXS

Receive Start. When this bit is set to 1, then the receive state ma-

chine begins operation. DRQ indications based upon RX FIFO

status are independent of the value of this bit. The receive state

machine is edge-sensitive, that is, this bit must be reset to 0 and set

again to 1 before a subsequent reception will begin. The receive

busy bit will be set in the Receive Status register (TIR17) to indicate

the state of reception. Resetting this bit to 0 during a reception will

not cause the current reception to be aborted. Receive abort is per-

formed with the RXRES bit.

TIR17: Receive Status Register

This register is the RX Status register. Indicates the cur-

rent status of the Receive portion of the TAI.

Bit

Name

Reset Value

Description

CRC32

CRC32 Good. The CRC32 machine has detected a good CRC and

has latched the byte count that was active at the time that the CRC

was good.

CRC8

CRC8 Good. The CRC8 machine has detected a good CRC and

has latched the byte count that was active at the time that the CRC

was good.

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