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DLP2010LC

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DLPS180 – MAY 2020

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Copyright © 2020, Texas Instruments Incorporated

(1)

JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

6.3 ESD Ratings

VALUE

UNIT

Electrostatic discharge

±2000

V

(1)

Recommended Operating Conditions are applicable after the DMD is installed in the final product.

(2)

The functional performance of the device specified in this datasheet is achieved when operating the device within the limits defined by

the Recommended Operating Conditions. No level of performance is implied when operating the device above or below the

Recommended Operating Conditions limits.

(3)

The following power supplies are all required to operate the DMD: VSS, VDD, VDDI, VOFFSET, VBIAS, and VRESET.

(4)

All voltage values are with respect to the ground pins (VSS).

(5)

VOFFSET supply transients must fall within specified maximum voltages.

(6)

To prevent excess current, the supply voltage delta |VDDI – VDD| must be less than specified limit.

(7)

To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than specified limit.

(8)

To prevent excess current, the supply voltage delta |VBIAS – VRESET| must be less than specified limit.

(9)

LS_CLK must run as specified to ensure internal DMD timing for reset waveform commands.

(10) Refer to the SubLVDS timing requirements in Timing Requirements.

6.4 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

(1) (2) (3)

MIN

NOM

MAX

UNIT

VDD

Supply voltage for LVCMOS core logic

Supply voltage for LPSDR low-speed

interface

1.65

1.8

1.95

V

VDDI

Supply voltage for SubLVDS receivers

1.65

1.8

1.95

V

VOFFSET

Supply voltage for HVCMOS and micromirror

9.5

10

10.5

V

VBIAS

Supply voltage for mirror electrode

17.5

18

18.5

V

VRESET

Supply voltage for micromirror electrode

–14.5

–14

–13.5

V

|VDDI–VDD|

0.3

V

|VBIAS–VOFFSET|

10.5

V

|VBIAS–VRESET|

33

V

CLOCK FREQUENCY

Clock frequency for low speed interface

108

120

MHz

Clock frequency for high speed interface

300

600

MHz

Duty cycle distortion DCLK

44%

56%

SubLVDS input differential voltage (absolute

value) Figure 9, Figure 10

150

250

350

mV

Common mode voltage Figure 9, Figure 10

700

900

1100

mV

SubLVDS voltage Figure 9, Figure 10

575

1225

mV

Line differential impedance (PWB/trace)

90

100

110

Ω

Internal differential termination resistance

Figure 11

80

100

120

Ω

100-Ω differential PCB trace

6.35

152.4

mm