22

DLP2010LC

DLPS180 – MAY 2020

www.ti.com

Product Folder Links: DLP2010LC

Submit Documentation Feedback

Copyright © 2020, Texas Instruments Incorporated

7.3 Feature Description

7.3.1 Power Interface

The power management component DLPA200x/DLPA3000, contains three 3 regulated DC supplies for the DMD

reset circuitry: VBIAS, VRESET and VOFFSET, as well as the two regulated DC supplies for the DLPC3470

controller.

7.3.2 Low-Speed Interface

The low speed interface handles instructions that configure the DMD and control reset operation. LS_CLK is the

low–speed clock, and LS_WDATA is the low speed data input.

7.3.3 High-Speed Interface

The purpose of the high-speed interface is to transfer pixel data rapidly and efficiently, making use of high speed

DDR transfer and compression techniques to save power and time. The high-speed interface uses differential

SubLVDS receivers for inputs, with a dedicated clock.

7.3.4 Timing

The data sheet provides timing test results at the device pin. For output timing analysis, the tester pin electronics

and its transmission line effects must be considered. Figure 14 shows an equivalent test load circuit for the

output under test. Timing reference loads are not intended as a precise representation of any particular system

environment or depiction of the actual load presented by a production test. TI recommends that system

designers use IBIS or other simulation tools to correlate the timing reference load to a system environment. The

load capacitance value stated is intended for characterization and measurement of AC timing signals only. This

load capacitance value does not indicate the maximum load the device is capable of driving.

7.4 Device Functional Modes

DMD functional modes are controlled by the DLPC3470 controller. See the DLPC3470 controller data sheet or

contact a TI applications engineer.

7.5 Optical Interface and System Image Quality Considerations

NOTE

TI assumes no responsibility for image quality artifacts or DMD failures caused by optical

system operating conditions exceeding limits described previously.

7.5.1 Optical Interface and System Image Quality

TI assumes no responsibility for end-equipment optical performance. Achieving the desired end-equipment

optical performance involves making trade-offs between numerous component and system design parameters.

Optimizing system optical performance and image quality strongly relate to optical system design parameter

trades. Although it is not possible to anticipate every conceivable application, projector image quality and optical

performance is contingent on compliance to the optical system operating conditions described in the following

sections.

7.5.1.1 Numerical Aperture and Stray Light Control

The angle defined by the numerical aperture of the illumination and projection optics at the DMD optical area is

typically the same. Ensure this angle does not exceed the nominal device micromirror tilt angle unless

appropriate apertures are added in the illumination or projection pupils to block out flat-state and stray light from

the projection lens. The micromirror tilt angle defines DMD capability to separate the "ON" optical path from any

other light path, including undesirable flat–state specular reflections from the DMD window, DMD border

structures, or other system surfaces near the DMD such as prism or lens surfaces. If the numerical aperture

exceeds the micromirror tilt angle, or if the projection numerical aperture angle is more than two degrees larger

than the illumination numerical aperture angle (and vice versa), contrast degradation and objectionable artifacts

in the display border and/or active area may occur.