TMS320VC5506 datasheet(29/119 Pages) TI1

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Functional Overview

October 2006 − Revised January 2008

SPRS375C

3.1

Memory

The 5506 supports a unified memory map (program and data accesses are made to the same physical space).

The total useable on-chip memory is 128K bytes (64K 16-bit words of RAM). There is 32K 16-bit words of ROM

used by the on-chip boot loader.

3.1.1 On-Chip Dual-Access RAM (DARAM)

The DARAM is located in the byte address range 000000h−00FFFFh and is composed of eight blocks of

8K bytes each (see Table 3−1). Each DARAM block can perform two accesses per cycle (two reads, two

writes, or a read and a write). DARAM can be accessed by the internal program, data, or DMA buses.

Table 3−1. DARAM Blocks

BYTE ADDRESS RANGE

MEMORY BLOCK

000000h − 001FFFh

DARAM 0†

002000h − 003FFFh

DARAM 1

004000h − 005FFFh

DARAM 2

006000h − 007FFFh

DARAM 3

008000h − 009FFFh

DARAM 4

00A000h − 00BFFFh

DARAM 5

00C000h − 00DFFFh

DARAM 6

00E000h − 00FFFFh

DARAM 7

† First 192 bytes are reserved for Memory-Mapped Registers (MMRs).

3.1.2 On-Chip Single-Access RAM (SARAM)

The SARAM is located at the byte address range 010000h−01FFFFh and is composed of 8 blocks of 8K bytes

each (see Table 3−2). Each SARAM block can perform one access per cycle (one read or one write). SARAM

can be accessed by the internal program, data, or DMA buses.

Table 3−2. SARAM Blocks

BYTE ADDRESS RANGE

MEMORY BLOCK

010000h − 011FFFh

SARAM 0

012000h − 013FFFh

SARAM 1

014000h − 015FFFh

SARAM 2

016000h − 017FFFh

SARAM 3

018000h − 019FFFh

SARAM 4

01A000h − 01BFFFh

SARAM 5

01C000h − 01DFFFh

SARAM 6

01E000h − 01FFFFh

SARAM 7

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