7534 Group

Rev.2.00

Jun 21, 2004

page 21 of 54

REJ03B0099-0200Z

Fig. 22 Block diagram of UART serial I/O

Fig. 23 Operation of UART serial I/O function

Serial I/O

qSerial I/O1

• Asynchronous serial I/O (UART) mode

Serial I/O1 can be used as an asynchronous (UART) serial I/O. A

dedicated timer (baud rate generator) is also provided for baud rate

generation when serial I/O1 is in operation.

Eight serial data transfer formats can be selected, and the transfer

formats to be used by a transmitter and a receiver must be identi-

cal.

Each of the transmit and receive shift registers has a buffer register

(the same address on memory). Since the shift register cannot be

written to or read from directly, transmit data is written to the trans-

mit buffer, and receive data is read from the respective buffer regis-

ters. These buffer registers can also hold the next data to be trans-

mitted and receive 2-byte receive data in succession.

By selecting “1” for continuous transmit valid bit (bit 2 of SIO1CON),

continuous transmission of the same data is made possible.

This can be used as a simplified PWM.

OE

PE FE

1/16

1/4

1/16

Data bus

Receive Buffer Register

Address

Receive Shift Register

Receive buffer full flag (RBF)

Receive interrupt request (RI)

ST Detector

SP Detector

UART Control Register

Character length selection bit

7-bit

8-bit

Clock Control Circuit

Baud Rate Generator

Division ratio 1/(n+1)

BRG count source selection bit

Transmit Buffer Register

Data bus

Transmit Shift Register

Address

Transmit shift register shift

completion flag (TSC)

Transmit buffer empty flag (TBE)

Transmit interrupt request (TI)

Character length selection bit

Transmit interrupt source selection bit

Continuous transmit valid bit

Serial I/O1 control register

Serial I/O1 status register

ST/SP/PA Generator

TSC=0

TBE=1

RBF=0

TBE=0

TBE=0

RBF=1

RBF=1

ST

SP

ST

SP

TBE=1

TSC=1*

ST

SP

ST

SP

1 : Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception).

2 : The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes “1”, depending on the setting of the transmit

interrupt source selection bit (TIC) of the serial I/O1 control register.

3 : The receive interrupt (RI) is set when the RBF flag becomes “1”.

4 : After data is written to the transmit buffer when TSC = 1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC = 0.

Notes

Transmit/Receive Clock

Transmit Buffer Register

Write Signal

Receive Buffer Register

Read Signal

* Generated at second bit in 2-stop -bit

mode

1 Start Bit

7 or 8 Data Bit

1 or 0 Parity Bit

1 or 2 Stop Bit