30

Am79D2251

Figure 19. PCM Highway Timing for XE = 1 (Transmit on Positive PCLK Edge)

GCI Timing Specifications

Notes:

1. The Data Clock (DCL) can be stopped in the high or low state without loss of information.

2. A temporary stoppage of DCL must not put the ISLAC into a state in which it does not respond to a software

reset command.

3. All frequency-dependent specifications are guaranteed for clock frequencies within ±100 PPM from

nominal.

Symbol

Signal

Parameter

Min

Typ

Max

Unit

DCL

Rise/fall time

60

ns

DCL

478

239

498

249

DCL

Pulse width

90

FS

Rise/fall time

60

FS

Setup time

70

FS

Hold time

50

FS

High pulse width

130

DU

Delay from DCL edge

100

DU

Delay from FS edge

150

DD

Data setup

twH+20

DD

Data hold

50

PCLK

FS

First

Bit

Second

Bit

V

IH

V

IL

V

IH

V

IL

26

24

23

27

22

25

28

34

35

DRA

33

30

First

Bit

DXA

V

OL

V

OH

TSCA

See Note 4

31

32

29

Time Slot Zero, Clock Slot Zero