82845MP datasheet(21/157 Pages) INTEL

21 / 157 page

Intel

® 82845MP/82845MZ Chipset-Mobile (MCH-M)

250687-002

Datasheet

2.1.

Host Interface Signals

Table 4. Host Interface Signal Descriptions

Signal Name

Type

Description

ADS#

I/O

AGTL+

Address Strobe: The system bus owner asserts ADS# to indicate the first of two

cycles of a request phase.

BNR#

I/O

AGTL+

Block Next Request: Used to block the current request bus owner from issuing a

new request. This signal is used to dynamically control the system bus pipeline

depth.

BPRI#

AGTL+

Bus Priority Request: The MCH-M is the only Priority Agent on the system bus. It

asserts this signal to obtain the ownership of the address bus. This signal has

priority over symmetric bus requests and will cause the current symmetric owner to

stop issuing new transactions unless the HLOCK# signal was asserted.

BR0#

I/O

AGTL+

Bus Request 0#: The MCH-M pulls the processor bus’ BR0# signal low during

CPURST#. The signal is sampled by the processor on the active-to-inactive

transition of CPURST#. The minimum setup time for this signal is 4 HCLKs. The

minimum hold time is 2 clocks and the maximum hold time is 20 HCLKs. BR0#

should be tristated after the hold time requirement has been satisfied.

CPURST#

AGTL+

CPU Reset: The CPURST# pin is an output from the MCH-M. The MCH-M asserts

CPURST# while RSTIN# (PCIRST# from ICH3-M) is asserted and for

approximately 1 ms after RSTIN# is deasserted. The CPURST# allows the

processor’s to begin execution in a known state.

DBSY#

I/O

AGTL+

Data Bus Busy: Used by the data bus owner to hold the data bus for transfers

requiring more than one cycle.

DEFER#

AGTL+

Defer Response: Signals that the MCH-M will terminate the transaction currently

being snooped with either a deferred response or with a retry response.

DBI[3:0]#

I/O

AGTL+ 4x

Dynamic Bus Inversion: Driven along with the HD[63:0]# signals. Indicates if the

associated signals are inverted or not. DBI[3:0]# are asserted such that the

number of data bits driven electrically low (low voltage) within the corresponding

16-bit group never exceeds 8.

DBI[x]#

Data Bits

DBI3#

HD[63:48]#

DBI2#

HD[47:32]#

DBI1#

HD[31:16]#

DBI0#

HD[15:0]#

DRDY#

I/O

AGTL+

Data Ready: Asserted for each cycle that data is transferred.

HA[31:3]#

I/O

AGTL+ 2x

Host Address Bus: HA[31:3]# connect to the system address bus. During

processor cycles the HA[31:3]# are inputs. The MCH-M drives HA[31:3]# during

snoop cycles on behalf of hub interface and AGP/Secondary PCI initiators.

HA[31:3]# are transferred at 2x rate. Note that the address is inverted on the

system bus.

HADSTB[1:0]#

I/O

AGTL+ 2x

Host Address Strobe: The source synchronous strobes used to transfer

HA[31:3]# and HREQ[4:0]# at the 2x transfer rate.

Strobe

Address Bits

HADSTB0#

HA[16:3]#, HREQ[4:0]#

HADSTB1#

HA[31:17]#

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