Data Sheet AS8446

Revision 1.8, Date 2005-03-17

Page 25 of 35

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

NOTE

Off threshold for Reset generation

Voff_PORS

2.1

3.5

4.5

V

Ramp up

Hysteresis of Reset signal

Hyst_PORS

0.1

0.8

V

Sleep / wake up system

The whole IC is put in sleep mode (power down mode) by the control signal SLEEP set via the Three Wire Interface (SLEEP =

high, content register R17).

The whole start up and sleep mode behavior is shown in figure 4.

In sleep mode the following actions are done:

-

the power FET driver output OUT is hold at low (VSS)

-

the oscillator, the charge pump and all other blocks are put in a high ohmic status

-

the 5 V regulator is switched off (no external supply at pin VDD, this way all devices on the motor regulator board supplied

by VDD, e.g. the

µP and the external temperature sensor, are powered down)

-

-

the total current consumption of the IC is less than 90

µA

Applying a “low”-pulse on the wake-up pin will wake up the IC.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

NOTE

Current Consumption in Sleep Mode

Ivbat_pd

90

µA

Current Consumption in Sleep Mode

(1)

Ivbat_pd27

(50)

µA

R17<0> = 1 (SLEEP =

high)

Note (1): only as information. Will not be tested.

Reference Current Generator

The reference current generator uses a bandgap based 1 V reference voltage to generate a buffered 1 V voltage reference at

pin Iref. A 22 k

Ω external resistor must be used to generate the 45 µA current reference.

PARAMETER

SYMBOL

MIN

TYP

MAX

UNIT

NOTE

Voltage at pin Iref

Vref

0.95

1.0

1.05

V

High Side Power FET Driver / Slew Rate Regulation

The supply voltage of this driver is about 10 V higher than the Vbat (n-channel power FET to drive) and is delivered by the on

chip charge pump at pin Vpump.

The Power FET driver is controlled in two different ways:

First by the digital output of the PWM generator of the

µP to realizing a certain duty cycle of the motor drive and so to regulate

the motor current, voltage or speed in a closed loop.

The driver output OUT is set to low (the motor is switched off) independently of the PWM signal under the following conditions:

•

over current condition:

The over current signal Poverc is set to high by the over

(Poverc = high

)

current detection unit and reset to low via the Three Wire Interface

•

under voltage condition of Vbat:

The under voltage signal PVunder is set and reset by the voltage

(PVunder = high)

monitor.

•

over voltage condition of Vbat:

The over voltage signal PVover is set and reset by the voltage

(PVover = high )

monitor.