Data Sheet AS8446

Revision 1.8, Date 2005-03-17

Page 22 of 35

Three -Wire

µP-Interface

Data transfer from the microprocessor or PC to the AS8446 and vice versa is accomplished by means of Three-Wire Interface.

The Three-Wire Interface of the AS8446 acts generally in slave mode. The master in the whole regulator board is either the

controlling

µP (normal regulator module in volume production) or a PC (development or field programming mode e.g. to realize

the EMC optimization).

All registers (see section Summary of all programmable registers (parameters, functions)) can be written and read by the

Three-Wire Interface.

Pin DATAout is high ohmic if the Three-Wire Interface chip select signal CS is not active (high).

During an over voltage situation the write access to the Three-Wire Interface is blocked.

Physical Interface

Supported modes, and bit order are shown in Figure 10 and Figure 11.

The DATAin signal must be valid with the rising edge of the clock Clk, the DATAout is valid with the falling edge of

the clock Clk.

The clock frequency should be as low as useful in the particular application. It is recommended not to use a clock

The MSB is always transmitted / received first.

LSB

CS

Clk

DATAin

DATAout

HEADER

DATA

MSB

>30 us

first frame

next

frame

LSB

MSB

>0.1 us

>30 us

Figure 10

Physical Interface of Three-Wire Interface in write mode

LSB

CS

Clk

DATAin

DATAout

HEADER

DATA

MSB

LSB

>30 us

first frame

next

frame

MSB

>30 us

Figure 11

Physical Interface of Three-Wire Interface in read mode