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AX68002QF датащи(PDF) 51 Page - ASIX Electronics Corporation

номер детали AX68002QF
подробное описание детали  2/4-Port USB KVM Switch SoC
PDF  57 Pages
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производитель  ASIX [ASIX Electronics Corporation]
домашняя страница  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX68002QF датащи(HTML) 51 Page - ASIX Electronics Corporation

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AX6800x
2/4-Port USB KVM Switch SoC
Copyright © 2015 ASIX Electronics Corporation. All rights reserved.
4.5.6 PS/2 Interface Timing
4.5.6.1 PS2 Host Receiving Data Timing
Symbol
Description
Min
Typ
Max
Units
TSU_S
Time from Data transition to falling edge of CLK
5
15
25
us
TOD
Time from rising edge of CLK to Data transition
5
15
TCH-5
us
TCL
Duration of CLK low (inactive)
30
40
50
us
TCH
Duration of CLK high (active)
30
40
50
us
TSU_S
Time from Data transition to falling edge of CLK
5
15
25
us
Figure 4-8: PS2 Host Receiving Data Timing Diagram and Table
4.5.6.2 Host Sending Data Timing
Symbol
Description
Min
Typ
Max
Units
TINH
Host bring CLK low to inhibit I/O (request to send)
(TINH
8 -
1) * 10
us
TCL
Duration of CLK low (inactive)
30
40
50
us
TCH
Duration of CLK high (active)
30
40
50
us
THLD
Time from low to high CLK transition when Device
samples Data
5
15
25
us
TSU_A
Time from falling edge of Data to falling edge of CLK
30
40
50
us
TDT
Time from rising edge of CLK11 to rising edge of Ack Bit -
-
50
8: The TINH is the Inhibit timing register.
Figure 4-9: PS2 Host Sending Data Timing Diagram and Table



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