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AX68002QF датащи(PDF) 49 Page - ASIX Electronics Corporation

номер детали AX68002QF
подробное описание детали  2/4-Port USB KVM Switch SoC
PDF  57 Pages
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производитель  ASIX [ASIX Electronics Corporation]
домашняя страница  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX68002QF датащи(HTML) 49 Page - ASIX Electronics Corporation

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AX6800x
2/4-Port USB KVM Switch SoC
Copyright © 2015 ASIX Electronics Corporation. All rights reserved.
4.5.5 High Speed SPI Interface Timing
4.5.5.1 Master Mode
Symbol
Description
Min
Typ
Max
Units
1
SCLK clock frequency
-
Fsys_clk
(SPIBRR + 1) * 2
-
MHz4
2
Setup time of SS[2:0] to the first SCLK
edge
-
(SPIDS * Tsys_clk5) + 0.5 * Tsclk6
-
ns
3
Hold time of SS[2:0] after the last SCLK
edge
-
(SPIDS * Tsys_clk) + N * Tsclk7
-
ns
4
Minimum idle time between transfers
(minimum SS[2:0] high time)
-
((32 * SPIDT + 6) * Tsys_clk) + (0.5 * Tsclk)
-
ns
5
MOSI data valid time, after SCLK edge
-
-
0.6
ns
6
MISO data setup time before SCLK edge
13.8
-
-
ns
7
MISO data hold time after SCLK edge
0
-
-
ns
8, 9
Bus drive time before SS[2:0] assertion
and after SS[2:0] de-assertion
-
0.5 * Tsclk
-
Figure 4-6: High Speed SPI Master Controller Timing Diagram and Table
4 Fsys_clk is the operating system clock frequency, 48 or 96MHz. The SPIBRR is SPI Baud Rate Register.
5 Tsys_clk = 1 / Fsys_clk, operating system clock period.
6 Tsclk = SCLK clock period.
7 The N = 0.5 when operating in Mode 0 or Mode 1; The N = 1 when operating in Mode 2 or Mode 3.
5
4
9
4
3
8
2
7
6
1
1
SCLK(output)
MOSI(output)
MISO(input)
SS0(output)



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