1

2

3

4

5

6

7

14

13

12

11

10

9

8

1CLR

1D

1PRE

1Q

1Q

GND

V

CC

2CLR

2D

2PRE

2Q

2Q

GND

V

CC

2CLK

1CLK

0.1 F

Bypass capacitor

placed close to

the device

Avoid 90°

corners for

signal lines

Recommend GND flood fill for

improved signal isolation, noise

reduction, and thermal dissipation

Unused output

left floating

Unused inputs

RX

I/O

Q

*Wake-up Pattern

13

SN74HCS72

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Copyright © 2020, Texas Instruments Incorporated

Typical Application (continued)

output current.

9.2.3 Application Curve

Figure 13. Application timing diagram

10 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the

disturbance. For this device, a 0.1-μF capacitor is recommended. It is acceptable to parallel multiple bypass caps

to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The

bypass capacitor should be installed as close to the power terminals as possible for best results.

11 Layout

11.1 Layout Guidelines

In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only

two inputs of a triple-input AND gate are used, or when only 3 of the 4 channels are used. Such input pins should

not be left completely unconnected because the unknown voltages result in undefined operational states.

Specified in Figure 14 are rules that must be observed under all circumstances. All unused inputs of digital logic

devices must be connected to a high or low bias to prevent them from floating. The logic level that must be

applied to any particular unused input depends on the function of the device. Generally they are tied to GND or

transceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted.

This pin keeps the input section of the I/Os from being disabled and floated.

11.2 Layout Example

Figure 14. Layout Example