82830MP datasheet(49/159 Pages) INTEL

49 / 159 page

Intel

® 830MP Chipset

298338-001

Datasheet

4.5.1.3

PCICMD - PCI Command Register - Device #0

Address Offset:

04-05h

Default Value:

0006h

Access:

Read/Write

Size

16 bits

Since GMCH-M Device #0 is the host-to-Hub Interface bridge, many of the PCI specific bits in this

Bit

Description

15:10

Reserved.

Fast Back-to-Back. This bit controls whether or not the master can do fast back-to-back write. Since

device #0 is strictly a target this bit is not implemented and is hardwired to 0. Writes to this bit position

have no affect.

Default Value=0.

SERR Enable (SERRE). This bit is a global enable bit for Device #0 SERR messaging. The GMCH-M

does not have an SERR# signal. The GMCH-M communicates the SERR# condition by sending an SERR

message to the ICH. If this bit is set to a 1, the GMCH-M is enabled to generate SERR messages over

Hub Interface for specific Device #0 error conditions that are individually enabled in the ERRCMD register.

The error status is reported in the ERRSTS and PCISTS registers. If SERRE is reset to 0, then the SERR

message is not generated by the GMCH-M for Device #0.NOTE: This bit only controls SERR messaging

for the Device #0. Device #1 has its own SERRE bit to control error reporting for error conditions occurring

on Device #1. The two control bits are used in a logical OR manner to enable the SERR Hub Interface

message mechanism.

Default Value=0.

Address/Data Stepping. Address/data stepping is not implemented in the GMCH-M, and this bit is

hardwired to 0. Writes to this bit position have no effect.

Default Value=0.

Parity Error Enable (PERRE). PERR# is not implemented by the GMCH-M, and this bit is hardwired to 0.

Writes to this bit position have no effect.

Default Value=0.

VGA Palette Snoop. The GMCH-M does not implement this bit and it is hardwired to a 0. Writes to this bit

position have no effect.

Default Value=0.

Memory Write and Invalidate Enable. The GMCH-M will never use this command and this bit is

hardwired to 0. Writes to this bit position have no effect.

Default Value=0.

Special Cycle Enable. The GMCH-M does not implement this bit and it is hardwired to a 0. Writes to this

bit position have no effect.

Default Value=0.

Bus Master Enable (BME). The GMCH-M is always enabled as a master on Hub Interface. This bit is

hardwired to a 1. Writes to this bit position have no effect.

Default Value=1.

Memory Access Enable (MAE). The GMCH-M always allows access to main memory. This bit is not

implemented and is hardwired to 1. Writes to this bit position have no effect.

Default Value=1.

I/O Access Enable (IOAE). This bit is not implemented in the GMCH-M and is hardwired to a 0. Writes to

this bit position have no effect. Default Value=0.

82830MP датащи(PDF) 49 Page - Intel Corporation

82830MP датащи(HTML) 49 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL