82830MP datasheet(39/159 Pages) INTEL

39 / 159 page

Intel

® 830MP Chipset

298338-001

Datasheet

window into the four bytes of configuration space specified by the contents of CONFIG_ADDRESS.

Any read or write to CONFIG_DATA will result in the GMCH-M translating the CONFIG_ADDRESS

into the appropriate configuration cycle. The GMCH-M is responsible for translating and routing the

CPU’s I/O accesses to the CONFIG_ADDRESS and CONFIG_DATA registers to internal GMCH-M

configuration registers, Hub Interface, or AGP/PCI1.

4.2.3

PCI Bus #0 Configuration Mechanism

The GMCH-M decodes the Bus Number (bits 23:16) and the Device Number fields of the

CONFIG_ADDRESS register. If the Bus Number field of CONFIG_ADDRESS is 0 the configuration

cycle is targeting a PCI Bus #0 device. The Host-Hub Interface Bridge entity within the GMCH-M is

hardwired as Device #0 on PCI Bus #0. The Host-AGP/PCI1 Bridge entity within the GMCH-M is

hardwired as Device #1 on PCI Bus #0. Configuration cycles to any of the GMCH-M’s internal

devices are confined to the GMCH-M and not sent over Hub Interface. Accesses to devices #3 to #31

will be forwarded over Hub Interface as Type 0 Configuration Cycles (see Hub Interface spec). A[1:0]

of the Hub Interface Request Packet for the Type 0 configuration cycle will be “00”. Bits 15:2 of the

CONFIG_ADDRESS register will be translated to the A[15:2] field of the Hub Interface Request

Packet of the configuration cycle as shown the figure below. The ICH3-M decodes the Type 0 access

and generates a configuration access to the selected internal device.

Figure 4. Hub Interface Type 0 Configuration Address Translation

Device Number

Function No.

0 0

Reserved

Type 0

Function No.

Device Number

Reserved

CONFIG_ADDRESS

Hub Interface Type 0

Configuration

Address Extension

cfg_hl0.vsd

4.2.4

Primary PCI and Downstream Configuration Mechanism

If the Bus Number in the CONFIG_ADDRESS is non-zero, and is less than the value programmed into

the GMCH-M’s device #1 SECONDARY BUS NUMBER register or greater than the value

programmed into the SUBORDINATE BUS NUMBER Register, the GMCH-M will generate a Type 1

Hub Interface Configuration Cycle. A[1:0] of the Hub Interface Request Packet for the Type 1

configuration cycle will be “01”. Bits 31:2 of the CONFIG_ADDRESS register will be translated to the

A[31:2] field of the Hub Interface Request Packet of the configuration cycle as shown in the figure

below. The ICH3-M compares the non-zero Bus Number with the SECONDARY BUS NUMBER and

SUBORDINATE BUS NUMBER registers of its P2P bridges to determine if the configuration cycle is

meant for Primary PCI, one of the ICH3-M’s Hub Interfaces, or a downstream PCI bus.

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