AM29BDS643D datasheet(20/46 Pages) AMD

20 / 46 page

Am29BDS643D

PRELI M INARY

Any commands written during the chip erase operation

are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that

occurs, the chip erase command sequence should be

reinitiated once that bank has returned to reading array

data, to ensure data integrity.

The host system may also initiate the chip erase

command sequence while the device is in the unlock

bypass mode. The command sequence is two cycles

cycles in length instead of six cycles. See Table 4 for

details on the unlock bypass command sequences.

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and

Figure 14 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 4 shows the address

and data requirements for the sector erase command

sequence.

The device does

not require the system to preprogram

prior to erase. The Embedded Erase algorithm auto-

matically programs and verifies the entire memory for

an all zero data pattern prior to electrical erase. The

system is not required to provide any controls or

timings during these operations.

After the command sequence is written, a sector erase

time-out of no less than 50 µs occurs. During the

time-out period, additional sector addresses and sector

erase commands may be written. Loading the sector

erase buffer may be done in any sequence, and the

number of sectors may be from one sector to all sec-

tors. The time between these additional cycles must be

less than 50 µs, otherwise erasure may begin. Any

sector erase address and command following the

exceeded time-out may or may not be accepted. It is

recommended that processor interrupts be disabled

during this time to ensure all commands are accepted.

The interrupts can be re-enabled after the last Sector

Erase command is written. Any command other than

Sector Erase or Erase Suspend during the time-out

period resets that bank to the read mode. The

system must rewrite the command sequence and any

additional addresses and commands.

The system can monitor DQ3 to determine if the sec-

tor erase timer has timed out (See the section on DQ3:

Sector Erase Timer.). The time-out begins from the ris-

ing edge of the final WE# pulse in the command

sequence.

When the Embedded Erase algorithm is complete, the

bank returns to reading array data and addresses are

no longer latched. Note that while the Embedded Erase

operation is in progress, the system can read data from

the non-erasing bank. The system can determine the

status of the erase operation by reading DQ7 or DQ6/

DQ2 in the erasing bank. Refer to the Write Operation

Status section for information on these status bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other commands

are ignored. However, note that a hardware reset

immediately terminates the erase operation. If that

occurs, the sector erase command sequence should

be reinitiated once that bank has returned to reading

array data, to ensure data integrity.

The host system may also initiate the sector erase

command sequence while the device is in the unlock

bypass mode. The command sequence is four cycles

cycles in length instead of six cycles.

Figure 2 illustrates the algorithm for the erase opera-

tion. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and

Figure 14 section for timing diagrams.

Erase Suspend/Erase Resume

Commands

The Erase Suspend command, B0h, allows the sys-

tem to interrupt a sector erase operation and then read

data from, or program data to, any sector not selected

for erasure. The bank address is required when writing

this command. This command is valid only during the

sector erase operation, including the minimum 50 µs

time-out period during the sector erase command se-

quence. The Erase Suspend command is ignored if

written during the chip erase operation or Embedded

Program algorithm.

When the Erase Suspend command is written during

the sector erase operation, the device requires a

maximum of 20 µs to suspend the erase operation.

However, when the Erase Suspend command is written

during the sector erase time-out, the device immedi-

ately terminates the time-out period and suspends the

erase operation.

After the erase operation has been suspended, the

bank enters the erase-suspend-read mode. The

system can read data from or program data to any

sector not selected for erasure. (The device “erase sus-

pends” all sectors selected for erasure.) Reading at any

address within erase-suspended sectors produces

status information on DQ7–DQ0. The system can use

DQ7, or DQ6 and DQ2 together, to determine if a

sector is actively erasing or is erase-suspended. Refer

to the Write Operation Status section for information on

these status bits.

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