AM29BDS643D datasheet(19/46 Pages) AMD

19 / 46 page

Am29BDS643D

PRELI M INARY

program command sequence. The unlock bypass

command sequence is initiated by first writing two

unlock cycles. This is followed by a third write cycle

containing the unlock bypass command, 20h. That

bank then enters the unlock bypass mode. A two-cycle

unlock bypass program command sequence is all that

is required to program in this mode. The first cycle in

this sequence contains the unlock bypass program

command, A0h; the second cycle contains the program

address and data. Additional data is programmed in

the same manner. This mode dispenses with the initial

two unlock cycles required in the standard program

command sequence, resulting in faster total program-

ming time. The host system may also initiate the chip

erase and sector erase sequences in the unlock

bypass mode. The erase command sequences are four

cycles in length instead of six cycles. Table 4 shows the

requ irem en ts fo r the unlock bypass co mm an d

sequences.

During the unlock bypass mode, only the Unlock

Bypass Program and Unlock Bypass Reset commands

are valid. To exit the unlock bypass mode, the system

mu st issu e the two -cycle un lo ck bypass re se t

command sequence. The first cycle must contain the

bank address and the data 90h. The second cycle

need only contain the data 00h. The bank then returns

to the read mode.

The device offers accelerated program operations

through the VPP input. When the system asserts VPP

on this input, the device automatically enters the

Unlock Bypass mode. The system may then write the

tw o- cy cle Un lock By pas s pr og r am c omman d

sequence. The device uses the higher voltage on the

VPP input to accelerate the operation. Note that sectors

must be unlocked using the Sector Lock/Unlock

command sequence prior to raising VPP to VID.

Figure 1 illustrates the algorithm for the program oper-

ation. Refer to the Erase/Program Operations table in

the AC Characteristics section for parameters, and

Figure 13 for timing diagrams.

Figure 1.

Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip erase

command sequence is initiated by writing two unlock

cycles, followed by a set-up command. Two additional

unlock write cycles are then followed by the chip erase

command, which in turn invokes the Embedded Erase

algorithm. The device does

not require the system to

preprogram prior to erase. The Embedded Erase algo-

rithm automatically preprograms and verifies the entire

memory for an all zero data pattern prior to electrical

erase. The system is not required to provide any con-

trols or timings during these operations. Table 4 shows

the address and data requirements for the chip erase

command sequence.

When the Embedded Erase algorithm is complete,

that bank returns to the read mode and addresses are

no longer latched. The system can determine the sta-

tus of the erase operation by using DQ7 or DQ6/DQ2.

Refer to the Write Operation Status section for infor-

mation on these status bits.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

Note: See Table 4 for program command sequence.

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