CS61584A datasheet(16/54 Pages) CIRRUS

16 / 54 page

CS61584A

DS261PP5

The line receiver contains all the necessary clock

and data recovery circuits.

The jitter attenuator meets AT&T 62411 require-

ments when using either a 1X or 8X reference

clock supplied by either a quartz crystal, crystal os-

cillator, or external reference at the REFCLK input

pin.

2.1

AT&T 62411 Customer Premises

Application

The AT&T 62411 specification applies to the T1

interface between the customer premises and the

carrier, and must be implemented by the customer

premises equipment in order to connect to the

AT&T network.

In 62411 applications, the management of jitter is a

very important design consideration. Typically, the

jitter attenuator is placed in the receive path of the

CS61584A to reduce the jitter input to the system

synchronizer. The jitter attenuated recovered clock

is used as the input to the transmit clock to imple-

ment a loop-timed system. A Stratum 4 (±32 ppm)

quality clock or better should be input to REFCLK.

Note that any jitter present on the reference clock

will not be filtered by the jitter attenuator.

2.2

Asynchronous Multiplexer

Application

Asynchronous multiplexers accept multiple T1/E1

lines (which are asynchronous to each other), and

combine them into a higher speed transmission rate

(e.g. M13 muxes and SONET muxes). In these sys-

tems, the jitter attenuator is placed in the transmit

path of the CS61584A to remove the gapped clock

jitter input by the multiplexer to TCLK. Because

the transmit clock is jittered, the reference clock to

the CS61584A is provided by an external source

operating at 1X or 8X the data rate. Because T1/E1

framers are not usually required in asynchronous

multiplexers, the B8ZS/AMI/HDB3 coders in the

CS61584A are activated to provide data interfaces

on TDATA and RDATA.

2.3

Synchronous Application

A typical example of a synchronous application is

a T1 card in a central office switch or a 0/1 digital

cross-connect system. These systems place the jit-

ter attenuator in the receive path to reduce the jitter

presented to the system. A Stratum 3 or better sys-

tem clock is input to the CS61584A transmit and

reference clocks.

3. TRANSMITTER

The transmitter accepts data from a T1 or E1 sys-

tem and outputs pulses of appropriate shape to the

line. The transmit clock (TCLK) and transmit data

(TPOS and TNEG, or TDATA) are supplied syn-

chronously. Data is sampled on the falling edge of

the TCLK input.

During Hardware mode operation, the configura-

tion pins (CON[3:0]) control transmitted pulse

shapes, transmitter source impedance, receiver

slicing level, and driver tristate as shown in

Table 1. During Host mode operation, the configu-

ration is established by the CON[3:0] bits in the

Control B registers. Typical output pulses are

shown in Figures 14 and 15. These pulse shapes are

fully pre-defined by circuitry in the CS61584A,

and are fully compliant with appropriate standards

when used with our application guidelines in stan-

dard installations. Both channels must be operated

at the same line rate (both T1 or both E1).

Host mode operation permits arbitrary transmit

pulse shapes to be created and downloaded to the

CS61584A. These custom pulse shapes can be used

to compensate for waveform degradation caused by

non-standard cables, transformers, or protection

circuitry (refer to the Arbitrary Waveform Regis-

ters section).

Note that the pulse width for Part 68 Option A

(324 ns) is narrower than the optimal pulse width

for DSX-1 (350 ns). The CS61584A automatically

adjusts the pulse width based on the configuration

selection.

CS61584A

DS261F1

CS61584A датащи(PDF) 16 Page - Cirrus Logic

CS61584A датащи(HTML) 16 Page - Cirrus Logic

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54

датащи скачать

ссылки URL