CS44210 datasheet(31/38 Pages) CIRRUS

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CS44210

DS539PP1

7. CONTROL PORT INTERFACE

The control port is used to load all the internal set-

tings. The operation of the control port may be

completely asynchronous with the audio sample

rate. However, to avoid potential interference prob-

lems, the control port pins should remain static if

no operation is required.

The CS44210 has MAP auto increment capability,

enabled by the INCR bit in the MAP register,

which is the MSB. If INCR is 0, then the MAP will

stay constant for successive writes. If INCR is set

to 1, then MAP will auto increment after each byte

is written, allowing block reads or writes of succes-

sive registers.

7.1 Format Selection

The control port has 2 formats: SPI and Two-Wire,

with the CS44210 operating as a slave device.

If Two-Wire operation is desired, AD0/CS should

be tied to VL or GND. If the CS44210 ever detects

a high to low transition on AD0/CS after power-up

and after the control port is activated, SPI format

will be selected.

7.2 Two-Wire Format

In Two-Wire Format, SDA is a bidirectional data

line. Data is clocked into and out of the part by the

clock, SCL, with a clock to data relationship as

shown in Figure 8. The receiving device should

send an acknowledge (ACK) after each byte re-

ceived. There is no CS pin. Pins AD0 and AD1

forms the partial chip address and should be tied to

VL or GND as required. The upper 6 bits of the 7-

bit address field must be 001000.

Note: MCLK is required during all two-wire

transactions. The Two-Wire format is compatible

with the I2C protocol.

7.2.1 Writing in Two-Wire Format

To communicate with the CS44210, initiate a

START condition of the bus. Next, send the chip

address. The eighth bit of the address byte is the

R/W bit (low for a write). The next byte is the

Memory Address Pointer, MAP, which selects the

lowed by the data to be written. To write multiple

registers, continue providing a clock and data,

waiting for the CS44210 to acknowledge between

each byte. To end the transaction, send a STOP

condition.

7.2.2 Reading in Two-Wire Format

To communicate with the CS44210, initiate a

START condition of the bus. Next, send the chip

address. The eighth bit of the address byte is the

R/W bit (high for a read). The contents of the reg-

ister pointed to by the MAP will be output after the

chip address. To read multiple registers, continue

providing a clock and issue an ACK after each

byte. To end the transaction, send a STOP condi-

tion.

7.3 SPI Format

In SPI format, CS is the CS44210 chip select sig-

nal, CCLK is the control port bit clock, CDIN is the

input data line from the microcontroller, CDOUT is

the output data line, and the chip address is

0010000. CS, CCLK and CDIN are all inputs and

data is clocked in on the rising edge of CCLK. CD-

OUT is an output and is three-stated when not ac-

tively outputting data.

7.3.1 Writing in SPI

Figure 9 shows the operation of the control port in

SPI format. To write to a register, bring CS low.

The first 7 bits on CDIN form the chip address and

must be 0010000. The eighth bit is a read/write in-

dicator (R/W), which must be low to write. The

next 8 bits form the Memory Address Pointer

(MAP), which is set to the address of the register

that is to be updated. The next 8 bits are the data

which will be placed into register designated by the

MAP. To write multiple registers, keep CS low and

continue providing clocks on CCLK. End the read

transaction by setting CS high.

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