PIN DESCRIPTIONS*

Clock Generator

XIN; XOUT - Crystal In; Crystal Out, Pins 5, 6.

A gate inside the chip is connected to these pins and can be used with a crystal to provide the

master clock for the device.

Alternatively, an external (CMOS compatible) clock can be

supplied into the XIN pin to provide the master clock for the device. Loss of clock will put the

device into a lower powered state (approximately 70% power reduction).

Serial Output I/O

CS - Chip Select, Pin 2.

This input allows an external device to access the serial port.

DRDY - Data Ready, Pin 20.

Data Ready goes low at the end of a digital filter convolution cycle to indicate that a new

output word has been placed into the serial port. DRDY will return high after all data bits are

shifted out of the serial port or two master clock cycles before new data becomes available if

the CS pin is inactive (high).

SDATA - Serial Data Output, Pin 19.

SDATA is the output pin of the serial output port. Data from this pin will be output at a rate

determined by SCLK. Data is output MSB first and advances to the next data bit on the falling

edges of SCLK. SDATA will be in a high impedance state when not transmitting data.

SCLK - Serial Clock Input, Pin 18.

A clock signal on this pin determines the output rate of the data from the SDATA pin. This pin

must not be allowed to float.

1

2

3

4

5

20

15

14

13

12

11

6

7

8

9

10

16

17

18

19

MULTIPLEXER SELECTION INPUT

A0

DRDY

DATA READY

CHIP SELECT

CS

SDATA

SERIAL DATA OUTPUT

CONVERT

CONV

SCLK

SERIAL CLOCK INPUT

CALIBRATE

CAL

VD+

POSITIVE DIGITAL POWER

CRYSTAL IN

XIN

DGND

DIGITAL GROUND

CRYSTAL OUT

XOUT

VA-

NEGATIVE ANALOG POWER

BIPOLAR/UNIPOLAR

BP/UP

VA+

POSITIVE ANALOG POWER

DIFFERENTIAL ANALOG INPUT

AIN1+

VREF-

VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG INPUT

AIN2+

VREF+

VOLTAGE REFERENCE INPUT

DIFFERENTIAL ANALOG INPUT

AIN1-

AIN2-

DIFFERENTIAL ANALOG INPUT

*Pinout applies to both PDIP and SOIC

CS5504

20

DS126F1

CS5504

20

DS126F2