CS5368 datasheet(31/39 Pages) CIRRUS

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DS624A1

CS5368

Bit[6] CLKMODE Setting this bit puts the part in 384X mode (divides XTI by 1.5), and clearing

the bit invokes 256X mode (divide XTI by 1.0 - pass through).

Bits[5:4] MDIV[1:0] Each bit selects an XTI divider. When either bit is low, an XTI divide by 1

function is selected. When either bit is HIGH, an XTI divide by 2 function is selected. With both

bits HIGH, XTI is divided by 4.

The table below shows the composite XTI division using both CLKMODE and MDIV[1:0].

Bits[3:2] DIF[1:0] Determine which data format the serial audio interface is using to clock out da-

ta.

DIF[1:0]

0x00 Left Justified format

0x01 I²S format

0x02 TDM format

0x03 TDM format

Bits[1:0] MODE[1:0] This bit field determines the device sample rate range and whether it is op-

erating as an audio clocking Master or Slave.

MODE[1:0]

0x00 Single-Speed Mode Master

0x01 Double-Speed Mode Master

0x02 Quad-Speed Mode Master

0x03 Slave Mode all speeds

5.4

02h (OVFL) Overflow Status Register

Default:

0xFF, no overflows have occurred.

Note:

This register interacts with Register 03h, the Overflow Mask Register.

The Overflow Status Register is used to indicate an individual overflow in a channel. If an overflow

condition on any channel is detected, the corresponding bit in this register is asserted (low) in ad-

dition to the open drain active low OVFL pin going low. Each overflow status bit is sticky and is

cleared only when read, providing full interrupt capability.

CLKMODE,MDIV[1],MDIV[0]

DESCRIPTION

000

Divide-by-1

100

Divide-by-1.5

001 or 010

Divide-by-2

101 or 110

Divide-by-3

011

Divide-by-4

111

Unused

R/W

765

210

ROVFL8

OVFL7

OVFL6

OVFL5

OVFL4

OVFL3

OVFL2

OVFL1

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