DS624A1

31

CS5368

4.7.1

of data are transmitted, odd channels first, then even. The MSB is always clocked out first.

In Slave Mode, if more than 32 SCLKs per channel are received from a Master controller, the CS5368 will

fill the longer frame with trailing zeroes. If fewer than 24 SCLKs per channel are received from a Master,

the CS5368 will truncate the serial data output to the number of SCLKs received.

4.7.2

TDM Format

In TDM Mode, all eight channels of audio data are serially clocked out during a single Frame Sync (FS)

cycle. The rising edge of FS signifies the start of a new TDM frame cycle. Each channel slot occupies 32

SCLKs, with the data left justified and with MSB first. TDM output data should both be latched on the rising

edge of SCLK within the specified setup and hold times.

To achieve maximum noise performance, SDOUT2/TDM should be loaded in the same manner as

SDOUT1/TDM. For the same reason, it is also recommended that the serial clock be synchronously de-

rived from the Master clock and be equal to 256xFS.

4.8

Overflow Detection

4.8.1

Stand-Alone Mode

The CS5368 includes overflow detection on all input channels. In Stand-Alone Mode, this information is

presented as open drain, active low on the OVFL pin. The pin will go to a logical low as soon as an over-

range condition in any channel is detected. The data will remain low, then timeout as specified in "Over-

flow Timeout" on page 19. After the timeout, the OVFL pin will return to a logical high if there has not been

any other overrange condition detected. Note that an overrange condition on any channel will restart the

timeout period.

4.8.2

Control-Port Mode

In Control-Port mode, the Overflow Status Register interacts with the Overflow Mask Register to provide

interrupt capability for each individual channel. See page 36 for details on these two registers.

4.9

Control Port Operation

The Control Port is used to read and write the internal device registers. It supports two industry standard

formats, I²C and SPI. The part is in I²C format by default. SPI mode is selected if there is ever a high-to-low

transition on the AD0/CS pin after the RST pin has been brought high.

4.9.1

SPI Mode

In SPI mode, CS is the CS5368 chip select signal; CCLK is the control port bit clock (input into the CS5368

from a controller); CDIN is the input data line from a controller; CDOUT is the output data line to a con-

troller. Data is clocked in on the rising edge of CCLK and is supplied on the falling edge of CCLK.

To write to a register, bring CS low. The first seven bits on CDIN form the chip address and must be

1001111. The eighth bit is a read/write indicator (R/W), which should be low to write. The next eight bits

form the Memory Address Pointer (MAP), which is set to the address of the register that is to be updated.

The next eight bits are the data which will be placed into the register designated by the MAP. During

writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a 47 k

sistor, if desired.