M41T81SM6FT datasheet(18/29 Pages) STMICROELECTRONICS

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M41T81S

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Century Bit

Bits D7 and D6 of Clock Register 03h contain the

CENTURY ENABLE Bit (CEB) and the CENTURY

Bit (CB). Setting CEB to a '1' will cause CB to tog-

gle, either from a '0' to '1' or from '1' to '0' at the turn

of the century (depending upon its initial state). If

CEB is set to a '0,' CB will not toggle.

Battery Low Warning

The M41T81S automatically performs battery volt-

age monitoring upon power-up and at factory-pro-

grammed time intervals of approximately 24

hours. The Battery Low (BL) Bit, Bit D4 of Flags

is found to be less than approximately 2.5V. The

BL Bit will remain asserted until completion of bat-

tery replacement and subsequent battery low

monitoring tests, either during the next power-up

sequence or the next scheduled 24-hour interval.

If a battery low is generated during a power-up se-

quence, this indicates that the battery is below ap-

proximately 2.5 volts and may not be able to

maintain data integrity. Clock data should be con-

sidered suspect and verified as correct. A fresh

battery should be installed.

If a battery low indication is generated during the

24-hour interval check, this indicates that the bat-

tery is near end of life. However, data is not com-

promised due to the fact that a nominal VCC is

supplied. In order to insure data integrity during

subsequent periods of battery back-up mode, the

battery should be replaced.

The M41T81S only monitors the battery when a

nominal VCC is applied to the device. Thus appli-

cations which require extensive durations in the

battery back-up mode should be powered-up peri-

odically (at least once every few months) in order

for this technique to be beneficial. Additionally, if a

battery low is indicated, data integrity should be

verified upon power-up via a checksum or other

technique.

Oscillator Fail Detection

If the Oscillator Fail Bit (OF) is internally set to '1,'

this indicates that the oscillator has either stopped,

or was stopped for some period of time and can be

used to judge the validity of the clock and date da-

ta.

In the event the OF Bit is found to be set to '1' at

any time other than the initial power-up, the STOP

Bit (ST) should be written to a '1,' then immediately

reset to '0.' This will restart the oscillator.

The following conditions can cause the OF Bit to

be set:

–

The first time power is applied (defaults to a '1'

on power-up).

–

The voltage present on VCC is insufficient to

support oscillation.

–

The ST Bit is set to '1.'

–

External interference of the crystal.

The OF Bit will remain set to '1' until written to logic

'0.' The oscillator must start and have run for at

least 4 seconds before attempting to reset the OF

Bit to '0.'

Oscillator Fail Interrupt Enable

If the Oscillator Fail Interrupt Bit (OFIE) is set to a

'1,' the IRQ pin will also be activated. The IRQ out-

put is cleared by resetting the OFIE or OF Bit to '0'

(not be reading the Flags Register).

Output Driver Pin

When the FT Bit, AFE Bit, SQWE Bit, and Watch-

dog Register are not set, the IRQ/FT/OUT/SQW

pin becomes an output driver that reflects the con-

tents of D7 of the Calibration Register. In other

words, when D7 (OUT Bit) and D6 (FT Bit) of ad-

dress location 08h are a '0,' then the IRQ/FT/OUT/

SQW pin will be driven low.

Note: The IRQ/FT/OUT/SQW pin is an open drain

which requires an external pull-up resistor.

Preferred Initial Power-on Default

Upon initial application of power to the device, the

following register bits are set to a '0' state: Watch-

dog Register; AFE; ABE; SQWE; OFIE; and FT.

The following bits are set to a '1' state: ST; OUT;

OF; and HT (see Table 5., page 18).

Table 5. Preferred Default Values

Note: 1. BMB0-BMB4, RB0, RB1.

2. State of other control bits undefined.

3. UC = Unchanged

Condition

Out

AFE

SQWE

ABE

WATCHDOG

OFIE

Initial Power-up(2)

1100

Subsequent Power-up

(with battery back-up)(3)

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