INT5130CS datasheet(7/38 Pages) ETC1

7 / 38 page

INTELLON CONFIDENTIAL

ADVANCE INFORMATION

Rev 8.1

INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet

SPI Master Port (Configuration PROM Interface)

SPI_DO

Output

SPI Master Data Out

INT5130 configuration data from the INT5130 to the

external E

2PROM.

SPI_DI

Input

SPI Master Data In

INT5130 configuration data from the external

2PROM to the INT5130.

SPI_CLK

Output

SPI Master Clock

Timing reference signal for SPI_DI and SPI_DO.

SPI_CS

Output

SPI Master Chip Select

Enables data transfers on the SPI Master Interface.

LED Control

LED0_N

Output

LED0_N: Collision Detection

Activate for a duration of 10 ms upon detection of a

collision.

LED1_N

Output

LED1_N: Activity Detection

Activate for a duration of 10 ms upon the receipt of

a properly addressed unicast or broadcast frame or

the transmission of a frame.

LED2_N

Output

LED2_N: Link Detection

Turns on when initialization is complete successfully

and “network” is established.

Analog Front End Interface

ADC_CLK

Output

ADC Clock

ADC clock output to the INT1000 Analog Conversion

IC.

DAC_CLK

Output

DAC Clock

DAC clock output to the INT1000 Analog Conversion

IC.

TX_EN

Output

Analog Front End Transmit Enable

Transmit Enable signal

RX_EN

Output

Analog Front End Receive Enable

Receive Enable signal

ADIO[9:0]

Input/Output

Analog/Digital I/O

ADC and DAC Data. Multiplexed parallel interface to

INT1000 Analog Conversion IC.

AGC[7:0]

Output

AGC Gain Select

Gain control driven by the INT5130 to set the AGC

level.

ADC_CAL

Output

ADC Calibrate

This pin must remain low during normal operation of

the ADC. It is pulsed high to request a calibration

cycle. The ADC_CAL minimum pulse width is 4

clock cycles. While this signal is high the ADC

calibration registers are cleared and the calibration

control circuitry is reset. The ADC_CAL pulse will

go high 217 clock cycles (2.6 ms) after power on

reset drops, and will remain high for the required 4

clock cycles.

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