Rev. 1.6
77
C8051F310/1/2/3/4/5/6/7
8.
CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in Section 17), an enhanced full-duplex UART (see description
in Section 15), an Enhanced SPI (see description in Section 16), 256 bytes of internal RAM, 128 byte
Special Function Register (SFR) address space (Section 8.2.6), and 29 Port I/O (see description in Sec-
tion 13). The CIP-51 also includes on-chip debug hardware (see description in Section 20), and interfaces
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
Figure 8.1. CIP-51 Block Diagram
- Fully Compatible with MCS-51 Instruction
Set
- 25 MIPS Peak Throughput with 25 MHz
Clock
- 0 to 25 MHz Clock Frequency
- 256 Bytes of Internal RAM
-29 Port I/O
- Extended Interrupt Handler
- Reset Input
- Power Management Modes
- On-chip Debug Logic
- Program and Data Memory Security
DATA BUS
TMP1
TMP2
PRGM. ADDRESS REG.
PC INCREMENTER
ALU
PSW
DATA BUS
MEMORY
INTERFACE
MEM_ADDRESS
D8
PIPELINE
BUFFER
DATA POINTER
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
MEM_CONTROL
CONTROL
LOGIC
A16
PROGRAM COUNTER (PC)
STOP
CLOCK
RESET
IDLE
POWER CONTROL
REGISTER
SFR
BUS
INTERFACE
SFR_ADDRESS
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
D8
D8
B REGISTER
ACCUMULATOR
D8
D8
D8
D8
MEM_WRITE_DATA
MEM_READ_DATA
SRAM
ADDRESS
REGISTER
SRAM
(256 X 8)
STACK POINTER
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