C8051F310 datasheet(52/224 Pages) ETC1

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C8051F310/1/2/3/4/5/6/7

Rev. 1.6

5.3.

Modes of Operation

ADC0 has a maximum conversion speed of 200 ksps. The ADC0 conversion clock is a divided version of

the system clock, determined by the AD0SC bits in the ADC0CF register (system clock divided by

(AD0SC + 1) for 0

≤ AD0SC ≤ 31).

5.3.1. Starting a Conversion

A conversion can be initiated in one of five ways, depending on the programmed states of the ADC0 Start

of Conversion Mode bits (AD0CM2-0) in register ADC0CN. Conversions may be initiated by one of the fol-

lowing:

Writing a ‘1’ to the AD0BUSY bit of register ADC0CN

A Timer 0 overflow (i.e., timed continuous conversions)

A Timer 2 overflow

A Timer 1 overflow

A rising edge on the CNVSTR input signal (pin P0.6)

A Timer 3 overflow

Writing a ‘1’ to AD0BUSY provides software control of ADC0 whereby conversions are performed "on-

demand". During conversion, the AD0BUSY bit is set to logic 1 and reset to logic 0 when the conversion is

complete. The falling edge of AD0BUSY triggers an interrupt (when enabled) and sets the ADC0 interrupt

flag (AD0INT). Note: When polling for ADC conversion completions, the ADC0 interrupt flag (AD0INT)

should be used. Converted data is available in the ADC0 data registers, ADC0H:ADC0L, when bit AD0INT

is logic 1. Note that when Timer 2 or Timer 3 overflows are used as the conversion source, Low Byte over-

flows are used if Timer 2/3 is in 8-bit mode; High byte overflows are used if Timer 2/3 is in 16-bit mode. See

Section “17. Timers” on page 183 for timer configuration.

Important Note About Using CNVSTR: The CNVSTR input pin also functions as Port pin P0.6. When the

CNVSTR input is used as the ADC0 conversion source, Port pin P0.6 should be skipped by the Digital

Crossbar. To configure the Crossbar to skip P0.6, set to ‘1’ Bit6 in register P0SKIP. See Section “13. Port

Input/Output” on page 125 for details on Port I/O configuration.

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