EM78P451SWM datasheet(26/54 Pages) EMC

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EM78P451S

8-Bit Microcontroller with OTP ROM

•

Product Specification (V1.0) 06.01.2004

(This specification is subject to change without further notice)

4.5.4 Programmed the related registers

As the SPI mode is defined, the related registers of this operation are shown in Table 2

and Table 3.

Table 2 Related Control Registers of the SPI Mode

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x0D

*SPIC/RD CES

SPIE

SRO

SSE

SBR2

SBR1

SBR0

0x0F

INTC/IOCF

TM1IE

SPIIE

EXIE

TCIE

SPIC: SPI Control Register.

Bit 7 (CES): Clock Edge Select bit

0 = Data shifts out on rising edge, and shifts in on falling edge. Data is on hold

during the low level.

1 = Data shifts out on falling edge, and shifts in on rising edge. Data is on hold

during the high level.

Bit 6 (SPIE):SPI Enable bit

0 = Disable SPI mode

1 = Enable SPI mode

Bit 5 (SRO):SPI Read Overflow bit

0 = No overflow.

1 = A new data is received while the previous data is still being on hold in the

SPIB register. Under this condition, the data in SPIS register will be destroyed.

To avoid setting this bit, users should read the SPIRB register even if the

transmission is implemented only.

NOTE

This can only occur under slave mode.

Bit 4 (SSE):SPI Shift Enable bit

0 = Reset as soon as the shifting is completed and the next byte is ready to shift.

1 = Start to shift, and stays on 1 while the current byte continues to transmit.

NOTE

This bit can be reset by hardware only.

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