EM78P451SWM datasheet(25/54 Pages) EMC

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EM78P451S

8-Bit Microcontroller with OTP ROM

Product Specification (V1.0) 06.01.2004

• 21

(This specification is subject to change without further notice)

The received byte will update the transmitted byte,

Both the RBF and RBFIF bits (located in Register 0x0C) will be set as the SPI

operation is completed.

Timing is shown in Fig.13 and14.

SDO/P93 (Pin 8):

Serial Data Out,

Transmit serially; the Most Significant Bit (MSB) first, Least Significant Bit (LSB)

last,

Program the same clock rate and clock edge to latch on both the master and slave

devices,

The received byte will update the transmitted byte,

The CES (located in Register 0x0D) bit will be reset, as the SPI operation is

completed.

Timing is shown in Fig.13 and 14.

SCK/P94 (Pin 9):

Serial Clock

Generated by a master device

Synchronize the data communication on both the SDI and SDO pins

The CES (located in Register 0x0D) is used to select the edge to communicate.

The SBR0~SBR2 (located in Register 0x0D) is used to determine the baud rate of

communication

The CES, SBR0, SBR1, and SBR2 bits have no effect in the slave mode

Timing is show in Fig.13 and 14

/SS/P95 (Pin 10):

Slave Select; negative logic,

Generated by a master device to signify the slave(s) to receive data,

Goes low before the first cycle of SCK appears, and remains low until the last

(eighth) cycle is completed,

Ignores the data on the SDI and SDO pins while /SS is high, because the SDO is

no longer driven.

Timing is shown in Fig.13 and Fig. 14.

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