©2019 Device Engineering Inc.

Page 9 of 12

DS-MW-01067-01 Rev G

2/7/2019

Table 6 Switching Characteristics (4)

SYMBOL

PARAMETER

CONDITIONS

(6, 7)

LIMITS

UNIT

MIN

MAX

SCLK frequency. (50% duty cycle) (5)

Maximum usable SCLK frequency = 1/(tp2 + tsu3)

VCC = 3.0 V

VCC = 4.5 V

VCC = 3.0 V

VCC = 4.5 V

4.8

24

2.8

10.7

MHZ

SCLK pulse width. (50% duty cycle)

VCC = 3.0 V

VCC = 4.5 V

100

20

ns

tsu1

Setup time, SCLK low to /CS↓.

VCC = 3.0 V

VCC = 4.5 V

100

50

ns

th1

Hold time, /CS↓ to SCLK↑.

VCC = 3.0 V

VCC = 4.5 V

20

20

ns

tsu2

Setup time, DIN valid to /CS↓.

1

35

us

th2

Hold time, /CS↓ to DIN not valid.

-1

us

tsu3

Setup time, SDIN valid to SCLK↑.

VCC = 3.0 V

VCC = 4.5 V

75

20

ns

th3

Hold time, SCLK↑ to SDIN not valid.

VCC = 3.0 V

VCC = 4.5 V

5

5

ns

tp1

Propagation delay, /CS↓ to DOUT valid. (1)

VCC = 3.0 V

VCC = 4.5 V

250

70

ns

tp2

Propagation delay, SCLK↑ to DOUT valid. (1)

VCC = 3.0 V

VCC = 4.5 V

250

100

ns

tp3

Propagation delay, /CS↑ to DOUT HI-Z. (1) (2) (3)

VCC = 3.0 V

VCC = 4.5 V

200

80

ns

tp4

Delay time between /CS active. (5)

VCC = 3.0 V

VCC = 4.5 V

25

25

ns

Cin

Maximum logic input pin Capacitance. (5)

10

pF

Cout

Maximum DOUT pin capacitance, output in HI-Z state. (5)

15

pF

Notes:

1.

DOUT loaded with 50 pF to GND.

2.

DOUT loaded with 1 kΩ to GND for Hi output, 1 kΩ to VCC for Low output.

3.

Timing measured at 25%VCC for “0” to Hi-Z, 75%VCC for “1” to Hi-Z.

4.

Sample tested on lot basis.

5.

Not tested

6.

Ta = -55 to +85 °C. VDD = +15 V, VIL = 0 V, VIH = VCC unless otherwise noted.

7.

Measurements made at 50%VCC.