www.ite.com.tw
IT8705F V0.4
71
Functional Description
9. Functional Description
9.1
LPC Interface
The IT8705F supports the peripheral site of the LPC I/F as described in the LPC Interface Specification
Rev.1.0 (Sept. 29,1997). In addition to the required signals (LAD3-0, LFRAME#, LRESET#, LCLK (PCICLK)),
the IT8705F also supports LDRQ#, SERIRQ and PME#.
9.1.1
LPC Transactions
The IT8705F supports some parts of the cycle types described in the LPC I/F specification. Memory read and
Memory write cycles are used for the Flash I/F. I/O read and I/O write cycles are used for the programmed I/O
cycles. DMA read and DMA write cycles are used for DMA cycles. All of these cycles are characteristic of the
single byte transfer.
For LPC host I/O read or write transactions, the Super I/O module processes a positive decoding, and the
LPC interface can respond to the result of the current transaction by sending out SYNC values on LAD[3:0]
signals or leave LAD[3:0] tri-state depending on its result.
For DMA read or write transactions, the LPC interface will make reactions according to the DMA requests
from the DMA devices in the Super I/O modules, and decides whether to ignore the current transaction or not.
The FDC and ECP are 8-bit DMA devices, so if the LPC host initializes a DMA transaction with data size of
16/32 bits, the LPC interface will process the first 8-bit data and response with a SYNC ready (0000b) which
will terminate the DMA burst. The LPC interface will then re-issue another LDRQ# message to assert DREQn
after finishing the current DMA transaction.
9.1.2
LDRQ# Encoding
The Super I/O module provides two DMA devices: the FDC and the ECP. The LPC Interface provides LDRQ#
encoding to reflect the DREQ[3:0] status. Two LDRQ# messages or different DMA channels may be issued
back-to-back to track DMA requests rapidly. But, four PCI clocks will be inserted between two LDRQ#
messages of the same DMA channel to guarantee that there is at least 10 PCI clocks for one DMA request to
change its status. (The LPC host will decode these LDRQ# messages, and sends those decoded DREQn to
the legacy DMA controller which runs at 4 MHz or 33/8 MHz).
9.2
Serialized IRQ
The IT8705F conforms to the specification of Serialized IRQ Support for PCI System, Rev. 6.0, September 1,
1995, to support the serialized IRQ feature, and is able to interface with most PC chipsets. The IT8705F
encodes the parallel interrupts to an SERIRQ which will be decoded by the chipset with built-in Interrupt
Controllers (two 8259 compatible modules).
9.2.1
Continuous Mode
When in the continuous mode, the SIRQ host initiates the Start frame of each SERIRQ sequence after
sending out the Stop frame by itself. (The next Start frame may or may not begin immediately after the Turn-
around State of current Stop frame.) The SERIRQ is always activated and SIRQ host keeps polling all the
IRQn and system events, even though no IRQn status is changed. The SERIRQ enter the continuous mode
following a system reset.
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
