ADF7012 datasheet(23/28 Pages) AD

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ADF7012

Rev. 0 | Page 23 of 28

915 MHZ OPERATION

The recommendations here are guidelines only. The design

should be subject to internal testing prior to FCC site testing.

Matching components need to be adjusted for board layout.

FCC 15.247 and FCC 15.249 are the main regulations governing

operation in the 902 MHz to 928 MHz Band. FCC 15.247

requires some form of spectral spreading. Typically, the

ADF7012 would be used in conjunction with the frequency

hopping spread spectrum (FHSS) or it may be used in

conjunction with the digital modulation standard which

requires large deviation frequencies. Output power of < 1 W

is tolerated on certain spreading conditions.

Compliance with FCC 15.249 limits the output power to

−1.5 dBm, but does not require spreading. There are many

different applications in this band, including remote controls

for security, sensor interrogation, metering, and home control.

Design Criteria

915.2MHz center frequency

FSK modulation

10 dBm output power

200 m range

Meets FCC 15.247

38.4 kbps data rate

The center frequency is 915.2 MHz. It is possible to operate

the VCO at this frequency. Figure 36 shows the inductor value

vs. center frequency. The inductor chosen is 1.6 nH. Coilcraft

inductors such as 0603-CS-1N6XJBU are recommended.

Additional hopping frequencies can easily be generated by

changing the N value.

Crystal and PFD

The phase noise requirement is such to ensure that the 20 dB

bandwidth requirements are met. These are dependant on the

channel spacing chosen. A typical channel spacing would be

400 kHz, which would allow 50 channels in 20 MHz and enable

the design to avoid the edges of the band.

The PFD is chosen so as to minimize spurious levels. There are

beat note spurious levels at 910 MHz and 920 MHz, but the

level is usually significantly less than the modulation power.

They are also attenuated quickly by the loop filter to ensure a

quick crystal power-up time.

PFD = 10 MHz − Power-Up Time 1.8 ms (approximately).

Figure 10 shows a typical power-on time for a 4 MHz crystal.

N-Divider

The N divider is determined as being:

Nint = 91

Nfrac = (2130)/4096

VCO divide-by-2 is not enabled

Deviation

The deviation is set to ±19.2 kHz so as to accommodate a

simple receiver architecture, and also to ensure the available

spectrum is used efficiently.

The modulation steps available are in 10 MHz/214 :

Modulation steps = 610 Hz

Modulation number = 19.2 kHz/610 Hz = 31.

Bias Current

Because low current is desired, a 3 mA VCO bias can be used

and still ensure oscillation at 928 MHz. Additional bias current

reduces any spurious noise, but increases current consumption.

A 3 mA bias current gives the best spurious vs. phase noise

trade-off.

The PA bias should be set to 5.5 mA to achieve 10 dBm power.

Loop Filter Bandwidth

The loop filter is designed with ADIsimPLL Version 2.5. A

data rate of 170 kHz is chosen, which allows for data rates of

> 38.4 kbps. It also attenuates the beat note spurs quickly to

ensure they have no effect on system performance.

Design of Harmonic Filter

The main requirement of the harmonic filter should ensure

that the third harmonic level is < −41.5 dBm. A fifth-order

Chebyshev filter is recommended to achieve this, and a

suggested starting point is given next. The Pi format is chosen

to minimize the number of inductors in the system.

Component Values—Crystal: 10 MHz

Loop Filter

Icp

1.44 mA

LBW

170 kHz

470 pF

12 nF

120 pF

470 V

1.8 kV

Matching

27 nH

6.2 nH

C14

470 pF

C15

Open

Harmonic Filter

8.2 nH

CF1

4.7 pF

CF2

6.8 pF

CF3

4.7 pF

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