PRELIMINARY

Rev. 3.0

- 5 -

July 2004

PRELIMINARY

K6R1004C1D

CMOS SRAM

TEST CONDITIONS

Parameter

Value

Input Pulse Levels

0V to 3V

Input Rise and Fall Times

3ns

Input and Output timing Reference Levels

1.5V

Output Loads

See below

Output Loads(B)

5pF*

480

Ω

+5.0V

* Including Scope and Jig Capacitance

Output Loads(A)

Ω

Ω

30pF*

* Capacitive Load consists of all components of the

test environment.

READ CYCLE*

* The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

K6R1004C1D-10

Unit

Min

Max

Read Cycle Time

10

-

ns

Address Access Time

-10

ns

Chip Select to Output

-10

ns

Output Enable to Valid Output

-5

ns

Chip Enable to Low-Z Output

3-

ns

Output Enable to Low-Z Output

0-

ns

Chip Disable to High-Z Output

05

ns

Output Disable to High-Z Output

05

ns

Output Hold from Address Change

3-

ns

Chip Selection to Power Up Time

0-

ns

Chip Selection to Power DownTime

-10

ns