CY28317PVC-2 datasheet(11/21 Pages) CYPRESS

11 / 21 page

CY28317-2

Document #: 38-07094 Rev. *B

Page 11 of 21

Byte 14: Programmable Frequency Select M-Value Register

Bit

Name

Default

Description

Bit 7

Pro_Freq_EN

Programmable output frequencies enabled

0 = Disabled

1 = Enabled

Bit 6

CPU_FSEL_M6

If Prog_Freq_EN is set, CY28317-2 will use the values programmed in

CPU_FSEL_N[7:0] and CPU_FSEL_M[6:0] to determine the CPU output fre-

quency. The new frequency will start to load whenever CPU_FSELM[6:0] is

updated.

The setting of the FS_Override bit determines the frequency ratio for CPU,

SDRAM and PCI. When it is cleared, CY28317-2 will use the same frequency

ratio stated in the Latched FS[4:0] register. When it is set, CY28317-2 will use

the frequency ratio stated in the SEL[4:0] register.

CY28317-2 supports programmable CPU frequencies ranging from 50 MHz

to 248 MHz.

Bit 5

CPU_FSEL_M5

Bit 4

CPU_FSEL_M4

Bit 3

CPU_FSEL_M3

Bit 2

CPU_FSEL_M2

Bit 1

CPU_FSEL_M1

Bit 0

CPU_FSEL_M0

Byte 15: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

–

Reserved

Bit 6

–

Reserved

Bit 5

–

Reserved

Bit 4

–

Reserved

Bit 3

–

Reserved

Bit 2

–

Vendor test mode

Reserved. Write with ‘0’

Bit 1

–

Vendor test mode

Test mode. Write with ‘1’

Bit 0

–

Vendor test mode

Test mode. Write with ‘1’

Byte 16: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

–

Reserved

Bit 6

–

Reserved

Bit 5

–

Reserved

Bit 4

–

Reserved

Bit 3

–

Reserved

Bit 2

–

Reserved

Bit 1

–

Reserved

Byte 17: Reserved Register

Bit

Pin#

Name

Default

Description

Bit 7

–

Reserved

Bit 6

–

Reserved

Bit 5

–

Reserved

Bit 4

–

Reserved

Bit 3

–

Reserved

Bit 2

–

Reserved

Bit 1

–

Reserved

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