7 / 21 page
CY28317-2
Document #: 38-07094 Rev. *B
Page 7 of 21
Byte 3: Control Register 3
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
1
Reserved
Bit 6
–
SEL_48MHz
0
0 = 24 MHz
1 = 48 MHz
Bit 5
27
48MHz
1
(Active/Inactive)
Bit 4
26
24_48MHz
1
(Active/Inactive)
Bit 3
–
Reserved
1
Reserved
Bit 2
31, 30
SDRAM4:5
1
(Active/Inactive)
Bit 1
34, 33
SDRAM2:3
1
(Active/Inactive)
Bit 0
37, 36
SDRAM0:1
1
(Active/Inactive)
Byte 4: Control Register 4
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved
Bit 6
–
Reserved
0
Reserved
Bit 5
–
Reserved
0
Reserved
Bit 4
–
Reserved
0
Reserved
Bit 3
–
Reserved
0
Reserved
Bit 2
–
Reserved
0
Reserved
Bit 1
–
Reserved
0
Reserved
Bit 0
–
Reserved
0
Reserved
Byte 5: Control Register 5
Bit
Pin#
Name
Default
Description
Bit 7
–
Reserved
0
Reserved
Bit 6
–
Reserved
0
Reserved
Bit 5
–
Reserved
0
Reserved
Bit 4
–
CPU1
Stop Control
0
0 = CPU1 will be stopped when
CPU_STOP# is active
1 = CPU1 will NOT be stopped when
CPU_STOP# is active
Bit 3
–
CPU0
Stop Control
0
0 = CPU0 will be stopped when CPU_STOP# is active
1 = CPU0 will NOT be stopped when CPU_STOP# is
active
Bit 2
–
CPUT and
CPUC Stop
Control
0
0 = CPUT and CPUC will be stopped when
CPU_STOP# is active
1 = CPUT and CPUC will NOT be stopped when
CPU_STOP# is active
Bit 1
2
REF1
1
(Active/Inactive)
Bit 0
3
REF0
1
(Active/Inactive)
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