AM29LV652D datasheet(13/55 Pages) SPANSION

13 / 55 page

October 29, 2004

Am29LV652D

PRELI M INARY

enabling the system to read the boot-up firmware from

the Flash memory.

If RESET# is asserted during a program or erase op-

eration, RY/BY# remains a “0” (busy) until the internal

reset operation is complete, which requires a time of

tREADY (during Embedded Algorithms). The system can

thus monitor RY/BY# to determine whether the reset

operation is complete. If RESET# is asserted when a

program or erase operation is not executing (RY/BY#

is “1”), the reset operation is completed within a time

of tREADY (not during Embedded Algorithms). The sys-

tem can read data tRH after RESET# returns to VIH.

Refer to the “AC Characteristics” on page 39 tables for

RESET# parameters and to Figure 14, on page 40 for

the timing diagram.

Output Disable Mode

When the OE# input is at VIH, output from the device is

disabled. The outputs are placed in the high

impedance state.

Table 2. Sector Address Table for CE# (Sheet 1 of 4)

Sector

A22

A21

A20

A19

A18

A17

A16

8-bit Address Range

(in hexadecimal)

SA0

0000000

000000–00FFFF

SA1

0000001

010000–01FFFF

SA2

0000010

020000–02FFFF

SA3

0000011

030000–03FFFF

SA4

0000100

040000–04FFFF

SA5

0000101

050000–05FFFF

SA6

0000110

060000–06FFFF

SA7

0000111

070000–07FFFF

SA8

0001000

080000–08FFFF

SA9

0001001

090000–09FFFF

SA10

0001010

0A0000–0AFFFF

SA11

0001011

0B0000–0BFFFF

SA12

0001100

0C0000–0CFFFF

SA13

0001101

0D0000–0DFFFF

SA14

0001110

0E0000–0EFFFF

SA15

0001111

0F0000–0FFFFF

SA16

0010000

100000–10FFFF

SA17

0010001

110000–11FFFF

SA18

0010010

120000–12FFFF

SA19

0010011

130000–13FFFF

SA20

0010100

140000–14FFFF

SA21

0010101

150000–15FFFF

SA22

0010110

160000–16FFFF

SA23

0010111

170000–17FFFF

SA24

0011000

180000–18FFFF

SA25

0011001

190000–19FFFF

SA26

0011010

1A0000–1AFFFF

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