AM29LV652D datasheet(35/55 Pages) SPANSION

35 / 55 page

October 29, 2004

Am29LV652D

PRELI M INARY

DQ2: Toggle Bit II

The “Toggle Bit II” on DQ2, when used with DQ6, indi-

cates whether a particular sector is actively erasing

(that is, the Embedded Erase algorithm is in progress),

or whether that sector is erase-suspended. Toggle Bit

II is valid after the rising edge of the final WE# pulse in

the command sequence.

DQ2 toggles when the system reads at addresses

within those sectors that have been selected for era-

sure. (The system may use either OE# or CE# or

CE2# to control the read cycles.) But DQ2 cannot dis-

tinguish whether the sector is actively erasing or is

erase-suspended. DQ6, by comparison, indicates

whether the device is actively erasing, or is in Erase

Suspend, but cannot distinguish which sectors are se-

lected for erasure. Thus, both status bits are required

for sector and mode information. Refer to Table 11, on

page 34 to compare outputs for DQ2 and DQ6.

Figure 6, on page 32 shows the toggle bit algorithm in

flowchart form, and the section “DQ2: Toggle Bit II” ex-

plains the algorithm. See also the DQ6: Toggle Bit I

subsection. Figure 19, on page 45 shows the toggle bit

timing diagram. Figure 20, on page 45 shows the dif-

ferences between DQ2 and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 6, on page 32 for the following discus-

sion. Whenever the system initially begins reading tog-

gle bit status, it must read DQ7–DQ0 at least twice in a

row to determine whether a toggle bit is toggling. Typi-

cally, the system would note and store the value of the

toggle bit after the first read. After the second read, the

system would compare the new value of the toggle bit

with the first. If the toggle bit is not toggling, the device

has completed the program or erase operation. The

system can read array data on DQ7–DQ0 on the fol-

lowing read cycle.

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should

then determine again whether the toggle bit is tog-

gling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer

toggling, the device has successfully completed the

program or erase operation. If it is still toggling, the de-

vice did not completed the operation successfully, and

the system must write the reset command to return to

reading array data.

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has

not gone high. The system may continue to monitor

the toggle bit and DQ5 through successive read cy-

cles, determining the status as described in the previ-

ous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start

at the beginning of the algorithm when it returns to de-

termine the status of the operation (top of Figure 6, on

page 32).

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time ex-

ceeded a specified internal pulse count limit. Under these

conditions DQ5 produces a “1,” indicating that the program

or erase cycle was not successfully completed.

The device may output a “1” on DQ5 if the system tries

to program a “1” to a location that was previously pro-

grammed to “0.” Only an erase operation can

change a “0” back to a “1.” Under this condition, the

device halts the operation, and when the timing limit is

exceeded, DQ5 produces a “1.”

Under both these conditions, the system must write

the reset command to return to the read mode (or to

the erase-suspend-read mode if the device was previ-

ously in the erase-suspend-program mode).

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not

erasure began. (The sector erase timer does not apply

to the chip erase command.) If additional sectors are

selected for erasure, the entire time-out also applies

after each additional sector erase command. When

the time-out period is complete, DQ3 switches from a

“0” to a “1.” If the time between additional sector erase

commands from the system can be assumed to be

less than 50 µs, the system need not monitor DQ3.

See also “Sector Erase Command Sequence” on

page 28

After the sector erase command is written, the system

should read the status of DQ7 (Data# Polling) or DQ6

(Toggle Bit I) to ensure that the device accepted the

command sequence, and then read DQ3. If DQ3 is

“1,” the Embedded Erase algorithm has begun; all fur-

ther commands (except Erase Suspend) are ignored

until the erase operation is complete. If DQ3 is “0,” the

device accepts additional sector erase commands. To

ensure the command is accepted, the system software

should check the status of DQ3 prior to and following

each subsequent sector erase command. If DQ3 is

high on the second status check, the last command

might not have been accepted.

Table 11, on page 34 shows the status of DQ3 relative

to the other status bits.

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