ADF41513 datasheet(28/30 Pages) AD

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ADF41513

Data Sheet

Rev. 0 | Page 28 of 30

APPLICATIONS INFORMATION

INITIALIZATION SEQUENCE

The following sequence of registers is the correct sequence for

initial power-up of the ADF41513 after the correct application

of voltages to the supply pins:

1. Register 13

2. Register 12

3. Register 11

4. Register 10

5. Register 9

6. Register 8

7. Register 7

8. Register 6

9. Register 5

10. Register 4

11. Register 3

12. Register 2

13. Register 1

14. Register 0

RF SYNTHESIZER: A WORKED EXAMPLE OF 25-BIT

FIXED MODULUS MODE

The following equation governs how to program the

synthesizer:

RFOUT = (INT + (FRAC1/225)) × fPFD

(7)

where:

RFOUT is the RF frequency output.

INT is the integer division factor.

FRAC1 is the fractional numerator.

fPFD is the PFD frequency.

For example, in a system where a 12.102 GHz RF frequency

output (RFOUT) is required and a 100 MHz reference frequency

input (REFIN) is available, the frequency resolution, fRES, is

fRES = REFIN/225

fRES = 100 MHz/225

= 2.98 Hz

From Equation 1 and Equation 2,

fPFD = (100 MHz × (1 + 0)/1) = 100 MHz

12.102 GHz = 100 MHz × (N + FRAC/225)

Calculating the INT and FRAC values,

INT = int(RFOUT/fPFD) = 121

FRAC1 = (int(RFOUT/fPFD) − INT) × 225 = 671088.64 ≈

671089

where:

INT is the 16-bit INT value in Register 0.

FRAC1 is the 25-bit FRAC1 value in Register 1.

int() makes an integer of the argument in parentheses.

Note that 671088.64 is rounded to 671,089, resulting in a small

frequency error. For exact frequency, use the variable

modulus mode.

RF SYNTHESIZER: A WORKED EXAMPLE OF

VARIABLE MODULUS MODE

The following is an example how to program the ADF41513

synthesizer:

RFOUT = fPFD × (INT + (FRAC1 + (FRAC2/MOD2))/225)

(8)

where:

RFOUT is the output frequency of the external VCO.

INT is a 16-bit value set by Bits[19:4] in Register 0. In Integer N

mode, INT is 20 to 511 for a 4/5 prescaler and 64 to 1023 for a 8/9

prescaler, and in fractional-N mode, INT is 23 to 511 for a 4/5

prescaler and 75 to 1023 for a 8/9 prescaler.

FRAC1 is a 25-bit value set by Bits[28:4] in Register 1.

FRAC2 is a 24-bit value set by Bits[27:4] in Register 3.

MOD2 is a 24-bit value set by Bits[27:4] in Register 4.

fPFD is the PFD frequency.

For example, in a system where a 12.102 GHz RFOUT is required

and a 100 MHz fPFD is available,

INT = int(RFOUT/fPFD) = 121

FRAC1 = int(((RFOUT/fPFD) – INT) × 225) = 671,088

where:

int() makes an integer of the argument in parentheses.

Remainder = FRAC2/MOD2 = 0.64

where:

FRAC2 = 64.

MOD2 = 100.

MODULUS

The choice of modulus (MOD) depends on the reference signal

(REFIN) available and the channel resolution (fRES) required at

the RF output.

REFERENCE DOUBLER AND REFERENCE DIVIDER

The on-chip reference doubler allows the input reference signal

to be doubled. Doubling is useful for increasing the PFD

comparison frequency. Setting the PFD frequency higher

improves the noise performance of the system. Doubling the

PFD frequency usually improves noise performance by 3 dB. It

is important to note that the reference input cannot operate

above 225 MHz when the reference doubler is on. The PFD

maximum operating frequency is 250 MHz (integer N mode) or

125 MHz (fractional-N mode) due to a limitation in the speed

of the Σ-Δ circuit.

The reference divide by 2 divides the reference signal by 2,

resulting in a 50% duty cycle PFD frequency.

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