Data Sheet

ADF41513

Rev. 0 | Page 17 of 30

REGISTER 0 (R0) MAP

Frequency changes occur only on a write to Register 0.

Variable Modulus

Register 0, Bit 28 = 0 enables the 25-bit fixed modulus.

Register 0, Bit 28 = 1 enables the variable modulus. See the

N Divider and R Counter section for more information.

INT Value

Register 0, Bits[19:4] set the INT value. See the N Divider and

R Counter section for more information.

REGISTER 1 (R1) MAP

DITHER2

Set Register 1, Bit 31 = 1 to enable the Σ-Δ modulator dither.

Enabling DITHER2 can reduce fractional spurs.

FRAC1

Register 1, Bits[28:4] set the FRAC1 value. See the N Divider

and R Counter section for more information. When using a

fixed modulus, Bits[28:4] are the FRAC value.

DB31

CONTROL

BITS

16-BIT INTEGER VALUE (INT)

RESERVED

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7 DB6

DB5 DB4

DB3

DB2

DB1 DB0

0

V1

0

0

0

0

0

0

0

0

0

0

N1

N2

N3

N4

N5

N6

N7

N8

N9

N10

N11

N12

N13

N14

N15

N16

C3(0)

C4(0)

C2(0) C1(0)

INT REGISTER (R0)

RESERVED

N16

N15

...

N2

N1

INTEGER WORD

INTEGER N MODE

PRESCALER 4/5: 20 ≤ INT ≤ 511

PRESCALER 8/9: 64 ≤ INT ≤ 1023

FRACTIONAL-N MODE

PRESCALER 4/5: 23 ≤ INT ≤ 511

PRESCALER 8/9: 75 ≤ INT ≤ 1023

0

0

...

0

0

NOT ALLOWED

0

0

...

0

1

NOT ALLOWED

0

0

...

1

0

NOT ALLOWED

0

0

...

1

1

NOT ALLOWED

.

.

...

.

.

.

20

.

.

...

.

.

.

0

0

...

0

1

21

0

.

0

1

.

1

.

1

.

1

.

1

.

1

.

1

.

1

.

1

.

1

.

1

.

1

.

NOT ALLOWED

...

1

0

1022

0

...

1

1

1023

...

...

0

0

NOT ALLOWED

V1 VARIABLE MODULUS

0

25-BIT FIXED MODULUS

VARIABLE MODULUS

1

N4

N3

0

0

0

0

0

0

0

0

.

.

.

.

0

1

1

1

1

1

0

0

N5

0

0

0

1

.

.

1

1

1

0

0

0

N14

0

0

0

0

.

.

0

0

N13

0

0

0

0

.

.

0

0

N12

0

0

0

0

.

.

0

0

0

0

0

0

0

0

0

0

0

0

0

0

N11

0

0

0

0

.

.

0

0

0

1

0

N10

0

0

0

0

.

.

0

1

1

0

0

...

0

0

0

1

1

Figure 23. Register 0 (R0) Map

FRAC1 REGISTER (R1)

DBB

DB31

CONTROL

BITS

25-BIT FRAC1 VALUE (FRAC1)

DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9

DB8

DB7 DB6

DB5 DB4

DB3 DB2

DB1 DB0

0

0

D1

F1

F2

F3

F4

F5

F6

F8

F7

F9

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

C3(0)

C4(0)

C2(0) C1(1)

NOTES

1. DBB MEANS DOUBLE-BUFFERED BITS.

F25

F24

...

F2

F1

FRAC1 WORD

0

0

...

0

0

0

0

0

...

0

1

1

0

0

...

1

0

2

0

0

...

1

1

3

.

.

...

.

.

.

.

.

...

.

.

.

.

.

...

.

.

.

1

1

...

0

0

33,554,428

1

1

...

0

1

33,554,429

1

1

...

1

0

33,554,430

1

1

...

1

1

33,554,431

D1

DITHER2

0

OFF

1

ON

Figure 24. Register 1 (R1) Map