High Speed CMOS Logic – 54HC30

 

 

Rev 1.0

7/5/2019

LIMITS

PARAMETER

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

SYMBOL

CONDITIONS

UNITS

FULL RANGE

4

25°C

85°C

2V

1.9

1.9

1.9

4.5V

4.4

4.4

4.4

6.0V

5.9

5.9

5.9

V

4.5V

3.98

3.84

3.70

Minimum High-Level

Output Voltage

6.0V

5.48

5.34

5.20

V

2V

0.1

0.1

0.1

4.5V

0.1

0.1

0.1

6.0V

0.1

0.1

0.1

V

4.5V

0.26

0.33

0.40

V

Maximum Low-Level

Output Voltage

6.0V

0.26

0.33

0.40

V

Maximum Input

Leakage Current

6.0V

GND

±0.1

±1.0

±1.0

µA

Maximum Quiescent

Supply Current

6.0V

GND,

2

20

40

µA

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2V

175

220

265

4.5V

35

44

53

Maximum Propagation

Delay, Any Input to

Output Y

6.0V

30

37

45

ns

2V

75

95

110

4.5V

15

19

22

Maximum Output Rise

and Fall Time, Any

Output

6.0V

13

16

19

ns

Maximum Input

Capacitance

-

-

10

10

10

pF

TYPICAL

Power Dissipation

Capacitance Per Gate

6

-

27

pF

 

5. Not production tested in die form, characterized by chip design and tested in package.

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