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Terminal Configuration and Functions

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SPRS953F – DECEMBER 2015 – REVISED MAY 2019

Table 4-2. Ball Characteristics(1) (continued)

BALL NUMBER [1]

BALL NAME [2]

SIGNAL NAME [3]

PN [4]

MUXMODE

[5]

TYPE [6]

BALL

RESET

STATE [7]

BALL

RESET

REL.

STATE [8]

BALL

RESET

REL.

MUXMODE

[9]

I/O

VOLTAGE

VALUE [10]

POWER

[11]

HYS [12]

BUFFER

TYPE [13]

PULL

UP/DOWN

TYPE [14]

DSIS [15]

C23

xref_clk3

1.8/3.3

vddshv3

Yes

Dual

Voltage

LVCMOS

PU/PD

mcasp2_axr11

mcasp1_axr7

mcasp4_ahclkx

mcasp8_ahclkx

vout2_de

hdq0

vin4a_de0

clkout3

timer16

gpio6_20

Driver off

(1) NA in this table stands for Not Applicable.

(2) For more information on recommended operating conditions, see Table 5-4, Recommended Operating Conditions.

(3) The pullup or pulldown block strength is equal to: minimum = 50 μA, typical = 100 μA, maximum = 250 μA.

(4) The output impedance settings of this IO cell are programmable; by default, the value is DS[1:0] = 10, this means 40

Ω. For more information on DS[1:0] register configuration, see the

Device TRM.

(5) IO drive strength for usb1_dp, usb1_dm, usb2_dp and usb2_dm: minimum 18.3 mA, maximum 89 mA (for a power supply vdda33v_usb1 and vdda33v_usb2 = 3.46 V).

(6) Minimum PU = 900 Ω, maximum PU = 3.090 kΩ and minimum PD = 14.25 kΩ, maximum PD = 24.8 kΩ.

For more information, see chapter 7 of the USB2.0 specification, in particular section Signaling / Device Speed Identification.

(7) In PUx / PDy, x and y = 60 to 200 μA.

The output impedance settings (or drive strengths) of this IO are programmable (34 Ω, 40 Ω, 48 Ω, 60 Ω, 80 Ω) depending on the values of the I[2:0] registers.

(8) The VOUT3 interface when multiplexed onto balls mapped to the VDDSHV6 supply rail is restricted to operating in 1.8V mode only (VDDSHV6 must be supplied with 1.8V). 3.3V mode is

not supported. This must be considered in the pin mux programming and VDDSHVx supply connections.

(9) The internal pull resistors for balls K7, M7, J5, K6, J4, J6, H4, H5 are permanently disabled when sysboot15 is set to 1 as described in the section Sysboot Configuration of the Device

TRM. If internal pull-up/down resistors are desired on these balls then sysboot15 should be set to 0. If gpmc boot mode is used with SYSBOOT15=1 (not recommended) then external

pull-downs should be implemented to keep the address bus at logic-0 value during boot since the gpmc ms-address bits are high-z during boot.

4.3

Multiplexing Characteristics

Table 4-3 describes the device multiplexing (no characteristics are available in this table).

NOTE

This table doesn't take into account subsystem multiplexing signals. Subsystem multiplexing signals are described in Section 4.4, Signal

Descriptions.

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