GPBA02A datasheet(15/21 Pages) GENERALPLUS

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GPBA02A

Proprietary & Confidential

JAN. 06, 2011

Version: 1.6

resistor port independently. If PA/B/Cx is expected to set as Input

with pull high resistor port, the corresponding Bx of 00H/01H/02H

(BUFA/B/C) and 08H/09H/0AH (ATTA/B/C) both should be set as1,

and the corresponding Bx of 04H/05H/06H (DIRA/B/C) should be

cleared as 0.

PAD

ATTx= 1

DIRx= 0

VDDIO

BUFx= 1

DATx

Input with pull low resistor (PL):

As shown in the above I/O Cell Configuration table and Control

Registers table, each I/O port can be set as Input with pull low

resistor port independently. If PA/B/Cx is expected to set as Input

with pull low resistor port, the corresponding Bx of 00H/01H/02H

(BUFA/B/C) should be set as 1, and the corresponding Bx of

04H/05H/06H (DIRA/B/C) and 08H/09H/0AH (ATTA/B/C) both

should be cleared as 0.

PAD

VSSIO

ATTx= 0

DIRx= 0

BUFx= 1

DATx

CMOS output high/low:

As is shown in the above I/O Cell Configuration table and Control

Registers table, each I/O port can be set as CMOS output port

independently. If PA/B/Cx is expected to set as CMOS output

port, the corresponding Bx of 08H/09H/0AH (ATTA/B/C) should be

configured as 0, and the corresponding Bx of 04H/05H/06H

(DIRA/B/C) should be configured as 1. In addition, if the host

writes 0 to corresponding Bx of 00H/01H/02H (BUFA/B/C), the

PA/B/Cx will output low.

And else if the host writes 1 to

corresponding Bx of 00H/01H/02H (BUFA/B/C), the PA/B/Cx will

output high. The register BUFA/B/C acts as output data buffer.

VSSIO

VDDIO

ATTx= 0

DIRx= 1

BUFx

BUFx= 0, output 0

BUFx= 1, output 1

DATx

PAD

Inverted CMOS output high/low:

As is shown in the above I/O Cell Configuration table and Control

Registers table, each I/O port can be set as CMOS output port

independently. If PA/B/Cx is expected to set as CMOS output

port, the corresponding Bx of 08H/09H/0AH (ATTA/B/C) and

04H/05H/06H (DIRA/B/C) should be configured as 1. In addition,

if the host writes 0 to corresponding Bx of 00H/01H/02H

(BUFA/B/C), the PA/B/Cx will output high. And else, if the host

writes 1 to corresponding Bx of 00H/01H/02H (BUFA/B/C), the

PA/B/Cx will output low. The register BUFA/B/C acts as output

data buffer. And it is an inverted buffer.

PAD

VSSIO

VDDIO

ATTx=1

DIRx= 1

BUFx

BUFx= 1, output 0

BUFx= 0, output 1

DATx

Inverted open drain NMOS output:

As is shown in the above I/O Cell Configuration table and Control

Registers table, each I/O port can be set as open drain NMOS

output port independently. If PA/B/Cx is expected to set as open

drain NMOS output port, the corresponding Bx of 00H/01H/02H

(BUFA/B/C) and 08H/09H/0AH (ATTA/B/C) should be cleared as 0,

and then if the host writes 1 to the corresponding Bx of

04H/05H/06H (DIRA/B/C), the PA/B/Cx will output low. And if the

host writes 0 to the corresponding Bx of 04H/05H/06H (DIRA/B/C),

the PA/B/Cx is floating. In this case, the register DIRx acts as the

output data buffer register.

And it is an inverted open drain

NMOS output port.

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