GPBA02A

© Generalplus Technology Inc.

Proprietary & Confidential

14

JAN. 06, 2011

Version: 1.6

PIN

Pull High/Low Resistance@VDDIO=5V

IN

OUT Current @VDDIO=3V

PC7

100K High/Low

Schmitt-Trigger(0.4/0.6 VDD)

-8/20mA

PC6

100K High/Low

Schmitt-Trigger(0.4/0.6 VDD)

-8/20mA

PC5

100K High/Low

Schmitt-Trigger(0.4/0.6 VDD)

-8/20mA

PC4

100K High/Low

Schmitt-Trigger(0.4/0.6 VDD)

-8/20mA

PC3

100K High/Low

Schmitt-Trigger(0.4/0.6 VDD)

-8/20mA

PC2

100K High/Low

Schmitt-Trigger(0.4/0.6 VDD)

-8/20mA

PC1

100K High/Low

Schmitt-Trigger(0.4/0.6 VDD)

-8/20mA

PC0

100K High/Low

Schmitt-Trigger(0.4/0.6 VDD)

-8/20mA

5.4.1. I/O Cell Configuration

Mode: output high, output low, input with PL, input with PH, input with high Z, open drain NMOS output, open drain PMOS output.

IO function:

5.4.2. Combination IO Status to Archive IO Function

IO status

Function

0

0

0

Floating(default)

Floating input

0

0

1

Pull low

Pull low input

1

0

1

Pull high

Pull high input

0

1

0

Output low

0

1

1

Output high

Buffer output

1

0

0

Floating

1

1

0

Output high

Open drain P-MOS output

1

0

1

Pull high

1

1

1

Output low

Wire AND (inverted)

0

1

0

Output low

0

0

0

Floating

Open drain N-MOS output (inverted)

0

0

1

Pull low

0

1

1

Output high

Wired OR

0

0

0

Floating

0

0

1

Pull low

Dynamic pull low input

1

0

0

Floating

1

0

1

Pull high

Dynamic pull high input

1

1

0

Output high

1

1

1

Output low

Inverted buffer output

Input with high Z:

As shown in the above I/O Cell Configuration table and Control

Registers table, the default values of all these registers are 0.

And the default states of all these I/O ports are input with high Z.

If PA/B/Cx is expected to set as input with high Z port (floating),

the

corresponding

Bx

of

00H/01H/02H

(BUFA/B/C)

and

04H/05H/06H (DIRA/B/C) both should be cleared as 0. In this

case, the values of corresponding ATTA/B/Cx bit do not have to

consider it.

PAD

ATTx= 0 or 1

DIRx= 0

BUFx= 0

DATx

Input with pull high resistor (PH):

As shown in the above I/O Cell Configuration table and Control

Registers table, each I/O port can be set as Input with pull high