GPL32611B

© Generalplus Technology Inc.

Proprietary & Confidential

12

Oct. 02, 2018

Version: 1.3

recognize the interactive game with sensor input.

The video-in

interface supports CCIR601/CCIR656 format with YUV or RGB

format.

The output format is frame-based and the input frame

rate does not need to synchronize with GPL32611B system clock.

5.7. Sound Process Unit (SPU)

The GPL32611B equips a 16-channel SPU.

Each channel of

SPU supports PCM8/ PCM16/ ADPCM36 and a dynamic volume

compressor is also embedded to enlarge the overall volume.

For

software application, GPL32611B is also available for MP3/ WMA

decode and other wide-band (sample rate >= 16KHz) low bit-rate

algorithm.

5.8. Video Output Interface

5.8.1. STN-LCD interface

The STN-LCD driver interface supports up to 320X240 LCD panel

and supports 1-bit or 4-bit data bus for monochrome/gray-scale

STN, as well as the Memory interface (i80 interface) type CSTN.

5.8.2. TFT-LCD interface

The GPL32611B supports TFT-LCD controller with resolution up to

1024x768.

The LCD/LCM interface includes parallel RGB, serial

delta

RGB,

serial

stripe

RGB,

CPU

(MPU

/

i80)

type,

CCIR601/CCIR656, as well as the built-in Timing Controller.

The

TFT-LCD controller mainly provides four to seven timing control

pins and 8 or 16 or 18 data pins to control external TFT panel and

they are VSYNC, HSYNC, DE, DCLK, POL, STV, STH and DATA.

It also supports image clipping, sliding windows and the following

image processing: histogram statistics for auto brightness and

contrast, programmable RGB gamma correction and color convert

matrix for various post-image processing.

5.8.3. TV encoder

The GPL32611B also supports TV composite output with both

NTSC and PAL mode.

The output resolution can be up to

720x480.

A 10-bit video DAC is embedded in GPL32611B and it

can utilize minimum system cost and best performance.

The

de-flicker function is also featured to reduce the flicker effect under

TV interlace mode.

5.8.4. Scaling engine

A powerful scaling engine is built to support both up-scaling and

down-scaling image and video to fit the screen resolution of TV or

TFT.

5.9. MPEG4 Decoder

The MPEG4 decoder supports MPEG4 simple profile and H.263

video decoding, which supports video resolution up to 720x480.

Besides, it also includes built-in de-blocking filter to removes

blocking artifacts in low bit-rate block-based video coding.

The

De-blocking filtering is considered as important task due to

improvement of visual quality in low bit-rate video coding.

The

MPEG4 decoder has real-time decoding with up to VGA@30fps.

5.10. JPEG CODEC

The JPEG CODEC is a high speed hard-wired engine, which

supports image resolution up to 64M pixels (8000x8000) and is

compatible with ISO/IEC 10918-1 baseline.

It supports two

AC/DC

programmable

Huffman

table

and

programmable

luminance/chrominance quantization table.

The JPEG Decoder

engine supports the following formats: YUV444, YUV422, YUV420,

YUV411 and YUV400 (gray mode).

It also features thumbnail

decoding, image clipping and image sub-sampling.

The JPEG

Encoder engine supports two formats: YUV422 and YUV420.

It

also features the CMOS Sensor data format encode.

For Motion

JPEG application, the JPEG CODEC has both real-time decoding

and encoding with up to VGA@30fps.

5.11. Interrupt

The GPL32611B has 32 IRQ (Interrupt request) sources and 10

FIQ (Fast Interrupt request) sources.

FIQ is the high-priority

interrupt and IRQ is the low-priority.

Hence, an IRQ can be

interrupted by a FIQ, but not by another IRQ.

A FIQ cannot be

interrupted by any other interrupt sources.

The priorities of 32

IRQ sources can be configured by programmers.

5.12. I/O

5.12.1. GPIO

GPL32611B has eight I/O ports - IOA, IOB, IOC, IOE, IOF, IOG,

IOH, and IOI.

Each I/O pin has its normal function and is

described in the signal description section.

When the normal

function of the I/O is disabled, it will switch to GPIO function

automatically.

The following diagram is a GPIO schematic.

Register

Control

logic

pull high

pull low

Pin pad

Buffer(R)

Data(R)

Port_Data(W)

Port_Buffer(W)

Port_DIR(R/W)

Port_ATTR(R/W)