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Die Size (Unsawn)

1450 x 1400

57 x 55

µm

mils

Minimum Bond Pad Size

120 x 120

4.72 x 4.72

µm

mils

Die Thickness

350 (±20)

13.78 (±0.79)

µm

mils

Top Metal Composition

Al 1%Si 1.1µm

Back Metal Composition

N/A – Bare Si

High Speed CMOS Logic – 54HC86

Quadruple 2-Input Exclusive OR Gate IC in bare die form

Low Input Current: 1µA

Output Drive Capability: 10 LSTTL loads

Outputs directly interface CMOS, NMOS and TTL

Operating Voltage Range: 2V to 6V

CMOS High Noise Immunity

Function compatible with 54LS86

Full Military Temperature Range.

Rev 1.0

21/11/17

Features:

Ordering Information

The following part suffixes apply:

No suffix - MIL-STD-883 /2010B Visual Inspection

“H” - MIL-STD-883 /2010B Visual Inspection

+ MIL-PRF-38534 Class H LAT

“K” - MIL-STD-883 /2010A Visual Inspection (Space)

+ MIL-PRF-38534 Class K LAT

LAT = Lot Acceptance Test.

For further information on LAT process flows see below.

www.siliconsupplies.com\quality\bare-die-lot-qualification

Supply Formats:

Mechanical Specification

Default – Die in Waffle Pack (400 per tray capacity)

Sawn Wafer on Tape – On request

Unsawn Wafer – On request

Die Thickness <> 350µm(14 Mils) – On request

Assembled into Ceramic Package – On request

The 54HC86 is fabricated using a 2.5µm 5V CMOS

process and has the same high speed performance of

LSTTL combined with CMOS low power consumption.

Device inputs are compatible with standard CMOS

outputs and with LSTTL outputs with the use of pull-up

resistors. Input and Output buffers enable low noise

and stable outputs. Inputs are also protected against

ESD and voltage transients. The device performs the

Boolean functions Y = A ⊕ B = AB + AB in positive

logic.

Description

Die Dimensions in µm (mils)

1450 (57)