High Speed CMOS Logic – 54HC86

 

 

Rev 1.0

21/11/17

LIMITS

 

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

1.9

1.9

 

1.9

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0V

100

125

150

3.0V

80

90

110

4.5V

20

25

31

Maximum Propagation

Delay, Input A or B to

Output Y

(Figure 1,2)

6.0V

17

21

26

ns

2.0V

75

95

110

3.0V

30

40

55

4.5V

15

19

22

Maximum Output Rise

and Fall Time,

Any Output

(Figure 1,2)

6.0V

13

16

19

ns

4.5V

4.4

4.4

4.4

V

6.0V

5.9

5.9

5.9

3.0V

2.48

2.34

2.20

4.5V

3.98

3.84

3.70

Minimum High-Level

Output Voltage

V

6.0V

5.48

5.34

5.20

2.0V

0.1

0.1

0.1

4.5V

0.1

0.1

0.1

6.0V

V

0.1

0.1

0.1

3.0V

0.26

0.33

0.40

4.5V

0.26

0.33

0.40

Maximum Low-Level

Output Voltage

V

6.0V

0.26

0.33

0.40

Maximum Input

Leakage Current

6.0V

±0.1

±1.0

±1.0

µA

Maximum Quiescent

Supply Leakage

Current

6.0V

1

10

40

µA

5. Not production tested in die form, characterized by chip design and tested in package.

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