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CMOS High Voltage Logic – CD4093B

Rev 1.0

21/11/17

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

5V

1.6

1.6

1.6

10V

3.4

3.4

3.4

15V

Input A or B;

5

5

5

V

5V

1.6

1.6

1.6

10V

3.4

3.4

3.4

Maximum

Hysteresis Voltage

3

15V

Input A and B;

5

5

5

V

5V

0.3

0.3

0.3

10V

1.2

1.2

1.2

15V

Input A or B;

1.6

1.6

1.6

V

5V

0.3

0.3

0.3

10V

1.2

1.2

1.2

Minimum Hysteresis

Voltage

5

15V

Input A and B;

1.6

1.6

1.6

V

 

TYPICAL

LIMITS

PARAMETER

SYMBOL

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

5V

380

380

760

10V

180

180

360

Maximum

Propagation Delay,

Input to Output

(Figure 1)

15V

130

130

260

ns

5V

200

200

400

10V

100

100

200

Maximum Output

Transition Time, Any

Output (Figure 1)

15V

80

80

160

ns

Maximum Input

Capacitance

-

5

7.5

7.5

pF

 

6. Not production tested in die form, characterized by chip design and tested in package.