HT560

I2S Input Stereo Class D Amplifier

Copyright©2018, Jiaxing Heroic Technology Co., Ltd

-3-

7/2018 – V1.0

12

LRCK

I

Word select clock for the digital signal that is active on the serial port's input

data line

13

DGND

G

Ground for digital circuitry (NOTE: This pin should be connected to the

system ground)

14

NC

-

Not connected inside the device (all "no connect" pins should be connected

to ground for best thermal performance, however they can be used as routing

channels if required.)

15

LIM

I

Selects mode of Digital Output Clipper or AGC

16

AVDD

P

Power supply for internal analog circuitry

17

PVDDB

P

Power Supply for internal power circuitry of Channel B

18

PVDDB

P

19

BSB+

BST

Connection point for the OUTB+ bootstrap capacitor, which is used to create

a power supply for the high-side gate drive for OUTB+

20

OUTB+

O

Positive pin for differential speaker amplifier output B

21

OUTB-

O

Negative pin for differential speaker amplifier output B

22

BSB-

BST

Connection point for the OUTB- bootstrap capacitor, which is used to create

a power supply for the high-side gate drive for OUTB-

23

PGND

G

Ground for power device circuitry (NOTE: This terminal should be

connected to the system ground)

24

BSA-

BST

Connection point for the OUTA- bootstrap capacitor, which is used to create

a power supply for the high-side gate drive for OUTA-

25

OUTA-

O

Negative pin for differential speaker amplifier output A

26

OUTA+

O

Positive pin for differential speaker amplifier output A

27

BSA+

BST

Connection point for the OUTA+ bootstrap capacitor, which is used to

create a power supply for the high-side gate drive for OUTA

28

PVDDA

P

Power Supply for internal power circuitry of Channel A

29

PVDDA

P

30

PVDDA

P

31

GGND

G

Ground for gate drive circuitry (this terminal should be connected to the

system ground)

32

GVDD

O

Voltage regulator derived from PVDD supply (NOTE: This pin is provided

as a connection point for filtering capacitors for this supply and must not be

used to power any external circuitry)

33

SFT_CLIP

I

Sets the maximum output voltage before clipping (Limiter Level)

34

ANA_REG

P

Voltage regulator derived from AVDD supply (NOTE: This terminal is

provided as a connection point for filtering capacitors for this supply and

must not be used to power any external circuitry)

35

VCOM

P

Bias voltage for internal PWM conversion block

36

ANA_REF

P

Connection point for internal reference used by ANA_REG and VCOM

/

EP

G

Provides both electrical and thermal connection from the device to the

board. A matching ground pad must be provided on the PCB and the

device connected to it via solder. For proper electrical operation, this

ground pad must be connected to the system ground.