PIC12F635ESLASHSS datasheet(170/196 Pages) MICROCHIP

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PIC12F635/PIC16F636/639

DS41232B-page 168

Preliminary

15.11 AC Characteristics: Analog Front-End for PIC16F639 (industrial, extended)

AC CHARACTERISTICS

Standard Operating Conditions (unless otherwise stated)

Supply Voltage

2.0V

≤ VDD ≤ 3.6V

Operating temperature

-40°C

≤ TAMB ≤ +85°C for industrial

-40°C

≤ TAMB ≤ +125°C for extended

LC Signal Input

Sinusoidal 300 mVPP

Carrier Frequency

125 kHz

LCCOM connected to VSS

Param

No.

Sym.

Characteristic

Min

Typ†

Max

Units

Conditions

VSENSE

LC Input Sensitivity

13.0

mVPP

VDD = 3.0V

Output enable filter disabled

AGCSIG = 0; MODMIN = 00

(50% modulation depth setting)

Input = Continuous Wave (CW)

Output = Logic level transition from low-to-

high at sensitivity level for CW input.

VDE_Q

Coil de-Q’ing Voltage -

RF Limiter (RFLM) must be active

3—

VDD = 3.0V, Force IIN = 5

μA

RFLM

RF Limiter Turn-on Resistance

(LCX, LCY, LCZ)

—

700

Ohm

VDD = 2.0V, VIN = 8 VDC

SADJ

Sensitivity Reduction

—

-30

—

VDD = 3.0V

No sensitivity reduction selected

Max reduction selected

Monotonic increment in attenuation value from

setting = 0000 to 1111 by design

VIN_MOD

Minimum Modulation Depth

75% ± 12%

50% ± 12%

25% ± 12%

12% ± 12%

VDD = 3.0V

CTUNX

LCX Tuning Capacitor

—

44.1

—

81.9

VDD = 3.0V,

Config. Reg. 1, bits <6:1> Setting = 000000

63 pF +/- 30%

Config. Reg. 1, bits <6:1> Setting = 111111

63 steps, 1 pF/step

Monotonic increment in capacitor value from

setting = 000000 to 111111 by design

CTUNY

LCY Tuning Capacitor

—

44.1

—

81.9

VDD = 3.0V,

Config. Reg. 2, bits <6:1> Setting = 000000

63 pF +/- 30%

Config. Reg. 2, bits <6:1> Setting = 111111

63 steps, 1 pF/step

Monotonic increment in capacitor value from

setting = 000000 to 111111 by design

FCARRIER

Carrier frequency

—

125

—

kHz

Characterized at bench.

FMOD

Input modulation frequency

—

kHz

Input data rate, characterized at bench.

Parameter is characterized but not tested.

†

Data in “Typ” column is at 3.0V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

Note 1:

Required output enable filter high time must account for input path analog delays = TOEH - TDR + TDF

Required output enable filter low time must account for input path analog delays (= TOEL + TDR - TDF)

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