PIC12F635ESLASHSS datasheet(77/196 Pages) MICROCHIP

77 / 196 page

Preliminary

DS41232B-page 75

PIC12F635/PIC16F636/639

9.2

Reading the EEPROM Data

Memory

To read a data memory location, the user must write the

address to the EEADR register and then set control bit

RD (EECON1<0>), as shown in Example 9-1. The data

is available, in the very next cycle, in the EEDAT

instruction. EEDAT holds this value until another read,

or until it is written to by the user (during a write

operation).

EXAMPLE 9-1:

DATA EEPROM READ

9.3

Writing to the EEPROM Data

Memory

To write an EEPROM data location, the user must first

write the address to the EEADR register and the data

to the EEDAT register. Then the user must follow a

specific sequence to initiate the write for each byte, as

shown in Example 9-2.

EXAMPLE 9-2:

DATA EEPROM WRITE

The write will not initiate if the above sequence is not

exactly followed (write 55h to EECON2, write AAh to

EECON2, then set WR bit) for each byte. We strongly

recommend that interrupts be disabled during this

code segment. A cycle count is executed during the

required sequence. Any number that is not equal to the

required cycles to execute the required sequence will

prevent the data from being written into the EEPROM.

Additionally, the WREN bit in EECON1 must be set to

enable write. This mechanism prevents accidental

writes to data EEPROM due to errant (unexpected)

code execution (i.e., lost programs). The user should

keep the WREN bit clear at all times, except when

updating EEPROM. The WREN bit is not cleared

by hardware.

After a write sequence has been initiated, clearing the

WREN bit will not affect this write cycle. The WR bit will

be inhibited from being set unless the WREN bit is set.

At the completion of the write cycle, the WR bit is

cleared in hardware and the EE Write Complete

Interrupt Flag bit (EEIF) is set. The user can either

enable this interrupt or poll this bit. The EEIF bit

(PIR1<7>) must be cleared by software.

9.4

Write Verify

Depending on the application, good programming

practice may dictate that the value written to the data

EEPROM should be verified (see Example 9-3) to the

desired value to be written.

EXAMPLE 9-3:

WRITE VERIFY

9.4.1

USING THE DATA EEPROM

The

data

EEPROM

high-endurance,

byte

addressable array that has been optimized for the

storage of frequently changing information (e.g.,

program variables or other data that are updated often).

The maximum endurance for any EEPROM cell is

specified as D120. D124 specifies a maximum number

of writes to any EEPROM location before a refresh is

required of infrequently changing memory locations.

9.4.2

EEPROM ENDURANCE

As an example, hypothetically, a data EEPROM is

64 bytes long and has an endurance of 1M writes. It

also has a refresh parameter of 10M writes. If every

memory location in the cell were written the maximum

number of times, the data EEPROM would fail after

64M write cycles. If every memory location, save 1,

were written the maximum number of times, the data

EEPROM would fail after 63M write cycles, but the one

remaining location could fail after 10M cycles. If proper

refreshes occurred, then the lone memory location

would have to be refreshed 6 times for the data to

remain correct.

BSF

STATUS,RP0

;Bank 1

BCF

STATUS,RP1

;

MOVLW

CONFIG_ADDR

;

MOVWF

EEADR

;Address to read

BSF

EECON1,RD

;EE Read

MOVF

EEDAT,W

;Move data to W

BSF

STATUS,RP0

;Bank 1

BCF

STATUS,RP1

;

BSF

EECON1,WREN

;Enable write

BCF

INTCON,GIE

;Disable INTs

MOVLW

55h

;Unlock write

MOVWF

EECON2

;

MOVLW

AAh

;

MOVWF

EECON2

;

BSF

EECON1,WR

;Start the write

BSF

INTCON,GIE

;Enable INTS

BSF

STATUS,RP0

;Bank 1

BCF

STATUS,RP1

;

MOVF

EEDAT,W

;EEDAT not changed

;from previous write

BSF

EECON1,RD

;YES, Read the

;value written

XORWF

EEDAT,W

BTFSS

STATUS,Z

;Is data the same

GOTO

WRITE_ERR

;No, handle error

;Yes, continue

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