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10

Oki Semiconductor

Radio Interface

The radio interface supports simple, flexible control of the radio and its synthesizer. The control signal

timing is programmable by the processor. Figure 4 shows the connection to a typical radio architecture.

Radio Interface Signal Descriptions

Pin Name

Direction

Description

RXC1

Open-collector/drain Output

When asserted reception is enabled. RXC1 is always asserted during reception. This signal is

programmable to be open-collector (active low) or open-drain (active high).

TXC, TXC2

Open-collector/drain Output

When asserted transmission is enabled. Both signals are programmable to be open-collector

(active low) or open-drain (active high). Transmit is only activated following a receive (where

Clear Channel Assessment is performed). The timing of TXC1 and TXC2 at the start of a transmit

is programmable from the deassertion of RXC1. RXC2 is typically used for TX Power Amplifier

switching, and its assertion depends on the power control mode selected in the MSM7712.

RADPWR

Open-collector/drain output

This pin is asserted to power up the radio circuitry (i.e. local oscillators) for reception. The pin

is programmable to be open-collector (active low) or open-drain (active high).

ANT

Open-collector output

This pin selects one of two antennas for transmission or reception.

SLICE

Open-collector/drain output

This control pin determines the response time constant of an analog data slicer when using the

internal modem with an analog data slicer circuit (options MSEL-0 or 1). This pin is program-

mable to be open-collector (active low) or open-drain (active high). The pin is asserted when

CCA has determined a valid IEEE 802.11 GH signal (preamble is detected).

Figure 4. Typical FH Radio Interface

RADPWR

RXC1

SLICE

RXD

RSSITH

DACEN

LKDET

SYNCLK

SYNDAT

SYNLEN

IFD[5:0]

TXC1

TXC2

ANT

Disc

-

+

D

CSN

DAC

1LO

2LO

DAC

LNA

PA

Radio

MSM7712