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6

Oki Semiconductor

Processor Interface Signal Descriptions

Pin Name

Direction

Description

PA[17:16]

Input

Provides the high address pins to the MSM7712. The usage depends on the shared memory size. The address

space usage of the MSM7712 is 256 kbytes comprising MSM7712 registers and shared RAM.

PCSN

Input

Provides a processor chip select to the MSM7712. From reset, this pin is ignored and all processor accesses

use the MSM7712. The pin can then be configured by software to be active high or active low.

PD[15:0]

Bidirectional

Provides the data bus and low addresses. The 80C86 and 80C186 processors have a multiplexed address/

data bus and are connected directly to PD [15:0]. The MSM7712 configuration is provided on these pins dur-

ing reset. During reset (HRST asserted), the processor is reset and these pins are configured as input pins.

The configuration is set by weak pull-up and pull-down resistors on PD [7:0]. Following reset and when the

processor is not reset, the bus operates normally. See the Configuration Section for detailed options.

PST[2:0]

Input

Provides Processor Status to the MSM7712. Typically this differentiates between memory and I/O reads and

writes.

PREAD

This pin is reserved for future product enhancements.

PUBE

Input

In conjunction with PD[0], this signal provides a decode of even byte, odd byte, or word accesses by the pro-

cessor. The MSM7712 registers are accessed as words and the processor and shared RAMs can be accessed

as bytes or words.

PCLKOUT

Input

Within a 80C186 processor-based system, CLKOUT should be connected to PCLKOUT pin. This is required

such that PREADYN timing requirements relative to CLKOUT are met.

PREADYN

Input

This pin signals the processor that the bus cycle is complete. The only accesses that potentially require wait

states are those to the shared RAM. The shared RAM is accessed by the MSM7712 host (via PCMCIA) and

processor on a priority basis. This means the shared RAM may be busy when the processor requests an ac-

cess and hence wait states are inserted until the shared RAM is available.

PINTN

Output

One interrupt is provided from the MSM7712 to the processor. A fixed interrupt vector is provided on the data

bus for interrupt acknowledge cycles. Although described as active low (by the xxxN convention), the pin state

is active high or low depending on the processor selected.

PRESETN

Output

The processor is reset via the host computer with this signal. From card reset, the processor is typically held

in reset until the program code is downloaded from the host. Although described as active low (by the xxxN

convention) the pin state is active high or low depending on the processor selected.

PCLK

Output

The processor clock is provided by the MSM7712. From power up PCLK is set at SCK divided by 8. A register

programs PCLK to be from SCK to SCK divided by 8. The PCLK frequency selection allows a processor to op-

erate at either low power or maximum performance. Within a 80C186 system, the processor is synchronized

to the MSM7712 by monitoring the processor CLKOUT signal and skipping PCLK periods if necessary. All pro-

cessor types must use this clock. The MSM7712 expects the processor bus interface timing to be synchro-

nized with this clock signal.

Note: SCLK is typically 16 MHz or 32 MHz depending on which modem and processor is being used.